SN75LVDS84

更新时间： 2024-11-19 22:53:31

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
14页	196K
描述
FLATLINKE TRANSMITTERS

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数据手册

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SN75LVDS84 数据手册

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

DGG PACKAGE

(TOP VIEW)

21:3 Data Channel Compression at up to

163 Million Bytes per Second Throughput

Suited for SVGA, XGA, or SXGA Data

Transmission From Controller to Display

With Very Low EMI

GND

21 Data Channels Plus Clock In

Low-Voltage TTL and 3 Data Channels Plus

Clock Out Low-Voltage Differential

GND

Operates From a Single 3.3-V Supply and

250 mW (Typ)

LVDSGND

Y0M

Y0P

Y1M

Y1P

D10

5-V Tolerant Data Inputs

ESD Protection Exceeds 6 kV

GND

SN75LVDS84 Has Falling Clock-Edge

Triggered Inputs, SN75LVDS85 Has Rising

Clock-Edge-Triggered Inputs

D11 12

D12 13

NC 14

37 LVDSV

36 LVDSGND

35 Y2M

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal

Pitch

D13

D14

GND

D15

D16

D17

Y2P

CLKOUTM

CLKOUTP

LVDSGND

PLLGND

Consumes Less Than 1 mW When Disabled

Wide Phase-Lock Input Frequency Range:

31 MHz to 68 MHz

PLLV

PLLGND

SHTDN

CLKIN

D20

No External Components Required for PLL

D18

D19

Outputs Meet or Exceed the Requirements

of ANSI EIA/TIA-644 Standard

GND

Improved Replacement for the DS90C561

NC – Not Connected

description

The SN75LVDS84 and SN75LVDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift

registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single

integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be

synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as

the SN75LVDS82 or SN75LVDS86.

When transmitting, data bits D0 – D20 are each loaded into registers of the SN75LVDS84 upon the falling edge

and into the registers of the SN75LVDS85 on the rising edge of the input clock signal (CLKIN). The frequency

of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The

threeserialstreamsandaphase-lockedclock(CLKOUT)arethenoutputtoLVDSoutputdrivers. Thefrequency

of CLKOUT is the same as the input clock, CLKIN.

†

AVAILABLE OPTIONS

LATCHING CLOCK EDGE

FALLING

RISING

SN75LVDS84DGG

SN75LVDS84DGGR

SN75LVDS85DGG

SN75LVDS85DGGR

†

The R suffix indicates taped and reeled packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...14

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与SN75LVDS84相关器件

型号	品牌	获取价格	描述	数据表
SN75LVDS84A	TI	获取价格	FLATLINKE TRANSMITTER
SN75LVDS84A_07	TI	获取价格	FLATLINK TRANSMITTER
SN75LVDS84ADGG	TI	获取价格	FLATLINKE TRANSMITTER
SN75LVDS84ADGGG4	TI	获取价格	FLATLINK TRANSMITTER
SN75LVDS84ADGGR	TI	获取价格	FLATLINK TRANSMITTER
SN75LVDS84ADGGRG4	TI	获取价格	FLATLINK TRANSMITTER
SN75LVDS84CDGG	TI	获取价格	LINE DRIVER, PDSO48
SN75LVDS84CDGGR	TI	获取价格	LINE DRIVER, PDSO48
SN75LVDS84DGG	TI	获取价格	FLATLINKE TRANSMITTERS
SN75LVDS84DGGG4	TI	获取价格	Flatlink™ 变送器 \| DGG \| 48 \| 0 to 70

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