5秒后页面跳转
捷配首页

Datasheet > 驱动程序和接口 > 线路驱动器或接收器> SN75LVDS86A
SN75LVDS86A PDF预览

SN75LVDS86A

更新时间： 2024-01-13 02:49:50
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
14页 186K
描述
FLATLINKE RECEIVER

阅读下载

中文翻译

获取价格

SN75LVDS86A 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP48,.3,20
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.19
差分输出：NO输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm湿度敏感等级：2
功能数量：3端子数量：48
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：8.7 ns接收器位数：3
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

SN75LVDS86A 数据手册

 浏览型号SN75LVDS86A的Datasheet PDF文件第2页浏览型号SN75LVDS86A的Datasheet PDF文件第3页浏览型号SN75LVDS86A的Datasheet PDF文件第4页浏览型号SN75LVDS86A的Datasheet PDF文件第5页浏览型号SN75LVDS86A的Datasheet PDF文件第6页浏览型号SN75LVDS86A的Datasheet PDF文件第7页 
SN75LVDS86A  
FLATLINK RECEIVER  
SLLS318A – NOVEMBER 1998 – REVISED MAY 1999  
DGG PACKAGE  
(TOP VIEW)  
3:21 Data Channel Expansion at up to  
163 Million Bytes per Second Throughput  
Suited for SVGA, XGA, or SXGA Display  
Data Transmission From Controller to  
Display With Very Low EMI  
D17  
D18  
V
CC  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
D16  
D15  
D14  
GND  
D13  
2
GND  
D19  
3
3 Data Channels and Clock Low-Voltage  
Differential Channels In and 21 Data and  
Clock Low-Voltage TTL Channels Out  
4
D20  
5
NC  
6
Operates From a Single 3.3-V Supply  
Tolerates 4-kV HBM ESD  
LVDSGND  
A0M  
V
7
CC  
D12  
D11  
D10  
GND  
8
A0P  
9
Packaged in Thin Shrink Small-Outline  
Package (TSSOP) With 20-Mil Terminal  
Pitch  
A1M  
10  
11  
12  
A1P  
37 D9  
36  
35 D8  
LVDSV  
CC  
Consumes Less Than 1 mW When Disabled  
LVDSGND 13  
A2M 14  
V
CC  
Wide Phase-Lock Input Frequency Range  
31 MHz to 68 MHz  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A2P  
CLKINM  
D7  
No External Components Required for PLL  
D6  
CLKINP  
GND  
D5  
Inputs Meet or Exceed the Standard  
Requirements of ANSI EIA/TIA-644  
Standard  
LVDSGND  
PLLGND  
D4  
PLLV  
D3  
Improved Replacement for the DS90C364  
and SN75LVDS86  
CC  
PLLGND  
SHTDN  
CLKOUT  
D0  
V
CC  
D2  
Improved Jitter Tolerance  
D1  
GND  
description  
The SN75LVDS86A FlatLink receiver contains  
three serial-in 7-bit parallel-out shift registers and  
four low-voltage differential signaling (LVDS) line  
receivers in a single integrated circuit. These  
NC – Not connected  
functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84,  
or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL  
synchronous data at a lower transfer rate.  
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input  
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The  
SN75LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).  
The SN75LVDS86A requires only four line-termination resistors for the differential inputs and little or no control.  
The data bus appears the same at the input to the transmitter and output of the receiver with the data  
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear  
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A  
low level on this signal clears all internal registers to a low level.  
The SN75LVDS86A is characterized for operation over ambient free-air temperatures of 0 C to 70 C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

下载PDF

SN75LVDS86A 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS86A TI

功能相似

 FLATLINK RECEIVER

与SN75LVDS86A相关器件

型号 品牌 获取价格 描述 数据表
SN75LVDS86ADGG TI

获取价格

 		FLATLINKE RECEIVER
SN75LVDS86ADGGG4 TI

获取价格

 		FLATLINK RECEIVER
SN75LVDS86ADGGR TI

获取价格

 		FLATLINK RECEIVER
SN75LVDS86ADGGRG4 TI

获取价格

 		FLATLINK RECEIVER
SN75LVDS86AQ TI

获取价格

 		FLATLINK RECEIVER
SN75LVDS86DGG TI

获取价格

 		FLATLINKE RECEIVER
SN75LVDS86DGGR TI

获取价格

 		FlatLink(TM) Receiver 48-TSSOP
SN75LVDS86DGGRG4 TI

获取价格

 		TRIPLE LINE RECEIVER, PDSO48, 0.20 MM PITCH, GREEN, PLASTIC, TSSOP-48
SN75LVDS88 TI

获取价格

 		TFT LCD PANEL TIMING CONTROLLER WITH LVDS INTERFACE
SN75LVDS88A TI

获取价格

 		TFT LCD PANEL TIMING CONTROLLER WITH LVDS INTERFACE

与SN75LVDS86A相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证