SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MAY 1999
DGG PACKAGE
(TOP VIEW)
3:21 Data Channel Expansion at up to 163
Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D17
D18
V
CC
1
48
47
46
45
44
43
42
41
40
39
38
D16
D15
D14
GND
D13
2
GND
D19
3
3 Data Channels and Clock Low-Voltage
Differential Channels In and 21 Data and
Clock Low-Voltage TTL Channels Out
4
D20
5
NC
6
Operates From a Single 3.3-V Supply and
250 mW (Typ)
LVDSGND
A0M
V
7
CC
D12
D11
D10
GND
8
A0P
9
5-V Tolerant SHTDN Input
A1M
10
11
12
ESD Protection Exceeds 4 kV on Bus Pins
A1P
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
37 D9
36
35 D8
LVDSV
CC
LVDSGND 13
A2M 14
V
CC
Consumes Less Than 1 mW When Disabled
15
16
17
18
19
20
21
22
23
24
34
33
32
31
30
29
28
27
26
25
A2P
CLKINM
D7
Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
D6
CLKINP
GND
D5
LVDSGND
PLLGND
No External Components Required for PLL
Open-Circuit Receiver Fail-Safe Design
D4
PLLV
D3
CC
Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
PLLGND
SHTDN
CLKOUT
D0
V
CC
D2
Improved Replacement for the DS90C562
D1
GND
description
The SN75LVDS86 FlatLink receiver contains
NC – Not Connected
three serial-in 7-bit parallel-out shift registers, a 7×
clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.
These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81,
’83, ’84, or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage TTL
(LVTTL) synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT).
The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low level on this signal clears all internal registers to a low level.
The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design such that when the inputs are
not connected to an LVDS driver, the receiver outputs go to a low-level. This occurs even when the line is
differentially terminated at the receiver inputs.
The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0 C to 70 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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