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SN75LVDS84DGGR PDF预览

SN75LVDS84DGGR

更新时间: 2024-11-20 13:00:47
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
14页 196K
描述
FlatLink™ Transmitter 48-TSSOP 0 to 70

SN75LVDS84DGGR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP48,.3,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.09差分输出:YES
驱动器位数:4高电平输入电流最大值:0.00002 A
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:12.5 mm
湿度敏感等级:2功能数量:1
端子数量:48最高工作温度:70 °C
最低工作温度:输出特性:TOTEM-POLE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:1.2 mm子类别:Line Driver or Receivers
最大压摆率:100 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:3.6 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

SN75LVDS84DGGR 数据手册

 浏览型号SN75LVDS84DGGR的Datasheet PDF文件第2页浏览型号SN75LVDS84DGGR的Datasheet PDF文件第3页浏览型号SN75LVDS84DGGR的Datasheet PDF文件第4页浏览型号SN75LVDS84DGGR的Datasheet PDF文件第5页浏览型号SN75LVDS84DGGR的Datasheet PDF文件第6页浏览型号SN75LVDS84DGGR的Datasheet PDF文件第7页 
SN75LVDS84, SN75LVDS85  
FLATLINK TRANSMITTERS  
SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999  
DGG PACKAGE  
(TOP VIEW)  
21:3 Data Channel Compression at up to  
163 Million Bytes per Second Throughput  
Suited for SVGA, XGA, or SXGA Data  
Transmission From Controller to Display  
With Very Low EMI  
D4  
D3  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
V
D2  
2
CC  
D5  
GND  
D1  
3
21 Data Channels Plus Clock In  
Low-Voltage TTL and 3 Data Channels Plus  
Clock Out Low-Voltage Differential  
D6  
4
GND  
D7  
D0  
5
NC  
6
Operates From a Single 3.3-V Supply and  
250 mW (Typ)  
D8  
LVDSGND  
Y0M  
Y0P  
Y1M  
Y1P  
7
V
8
CC  
D9  
D10  
9
5-V Tolerant Data Inputs  
10  
11  
ESD Protection Exceeds 6 kV  
GND  
SN75LVDS84 Has Falling Clock-Edge  
Triggered Inputs, SN75LVDS85 Has Rising  
Clock-Edge-Triggered Inputs  
D11 12  
D12 13  
NC 14  
37 LVDSV  
CC  
36 LVDSGND  
35 Y2M  
Packaged in Thin Shrink Small-Outline  
Package (TSSOP) With 20-Mil Terminal  
Pitch  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
D13  
D14  
GND  
D15  
D16  
D17  
Y2P  
CLKOUTM  
CLKOUTP  
LVDSGND  
PLLGND  
Consumes Less Than 1 mW When Disabled  
Wide Phase-Lock Input Frequency Range:  
31 MHz to 68 MHz  
PLLV  
CC  
V
PLLGND  
SHTDN  
CLKIN  
D20  
No External Components Required for PLL  
CC  
D18  
D19  
Outputs Meet or Exceed the Requirements  
of ANSI EIA/TIA-644 Standard  
GND  
Improved Replacement for the DS90C561  
NC – Not Connected  
description  
The SN75LVDS84 and SN75LVDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift  
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single  
integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be  
synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as  
the SN75LVDS82 or SN75LVDS86.  
When transmitting, data bits D0 – D20 are each loaded into registers of the SN75LVDS84 upon the falling edge  
and into the registers of the SN75LVDS85 on the rising edge of the input clock signal (CLKIN). The frequency  
of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The  
threeserialstreamsandaphase-lockedclock(CLKOUT)arethenoutputtoLVDSoutputdrivers. Thefrequency  
of CLKOUT is the same as the input clock, CLKIN.  
AVAILABLE OPTIONS  
LATCHING CLOCK EDGE  
FALLING  
RISING  
SN75LVDS84DGG  
SN75LVDS84DGGR  
SN75LVDS85DGG  
SN75LVDS85DGGR  
The R suffix indicates taped and reeled packaging.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN75LVDS84DGGR 替代型号

型号 品牌 替代类型 描述 数据表
DS90C363BMT/NOPB TI

类似代替

+3.3V 可编程 LVDS 发送器 18 位平板显示器 (FPD) 链路 - 65MHz
DS90C365AMT/NOPB TI

类似代替

+3.3V 可编程 LVDS 发送器 18 位平板显示器链路 - 87.5MHz | DG
SN65LVDS95DGG TI

类似代替

LVDS SERDES TRANSMITTER

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