Datasheet > SN75LVDS84A_07

SN75LVDS84A_07

更新时间： 2024-01-15 08:51:35

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德州仪器 - TI		/
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16页	243K
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FLATLINK TRANSMITTER

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数据手册

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SN75LVDS84A_07 数据手册

SN75LVDS84A, SN65LVDS84AQ

FLATLINK TRANSMITTER

SLLS354E – MAY 1999 – REVISED JANUARY 2001

DGG PACKAGE

(TOP VIEW)

21:3 Data Channel Compression at up to

196 Million Bytes per Second Throughput

Suited for SVGA, XGA, or SXGA Data

Transmission From Controller to Display

With Very Low EMI

GND

21 Data Channels Plus Clock In

Low-Voltage TTL Inputs and 3 Data

Channels Plus Clock Out Low-Voltage

Differential Signaling (LVDS) Outputs

GND

LVDSGND

Y0M

Y0P

Y1M

Y1P

Operates From a Single 3.3-V Supply and

89 mW (Typ)

D10

Ultralow-Power 3.3-V CMOS Version of the

SN75LVDS84. Power Consumption About

One Third of the ’LVDS84

GND

D11 12

D12 13

NC 14

37 LVDSV

36 LVDSGND

35 Y2M

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20 Mil Terminal

Pitch

D13

D14

GND

D15

D16

D17

Y2P

CLKOUTM

CLKOUTP

LVDSGND

PLLGND

Consumes Less Than 0.54 mW When

Disabled

Wide Phase-Lock Input Frequency Range:

31 MHz to 75 MHz

PLLV

No External Components Required for PLL

PLLGND

SHTDN

CLKIN

D20

Outputs Meet or Exceed the Requirements

of ANSI EIA/TIA-644 Standard

D18

D19

GND

SSC Tracking Capability of 3% Center

Spread at 50-kHz Modulation Frequency

NC – Not Connected

Improved Replacement for SN75LVDS84

and NSC’s DS90CF363A 3-V Device

Available in Q-Temp Automotive

High Reliability Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

description

The SN75LVDS84AandSN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift

registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair

conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.

The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The

threeserialstreamsandaphase-lockedclock(CLKOUT)arethenoutputtoLVDSoutputdrivers. Thefrequency

of CLKOUT is the same as the input clock, CLKIN.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...16

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与SN75LVDS84A_07相关器件

型号	品牌	获取价格	描述	数据表
SN75LVDS84ADGG	TI	获取价格	FLATLINKE TRANSMITTER
SN75LVDS84ADGGG4	TI	获取价格	FLATLINK TRANSMITTER
SN75LVDS84ADGGR	TI	获取价格	FLATLINK TRANSMITTER
SN75LVDS84ADGGRG4	TI	获取价格	FLATLINK TRANSMITTER
SN75LVDS84CDGG	TI	获取价格	LINE DRIVER, PDSO48
SN75LVDS84CDGGR	TI	获取价格	LINE DRIVER, PDSO48
SN75LVDS84DGG	TI	获取价格	FLATLINKE TRANSMITTERS
SN75LVDS84DGGG4	TI	获取价格	Flatlink™ 变送器 \| DGG \| 48 \| 0 to 70
SN75LVDS84DGGR	ROCHESTER	获取价格	LINE DRIVER, PDSO48, GREEN, PLASTIC, TSSOP-48
SN75LVDS84DGGR	TI	获取价格	FlatLink™ Transmitter 48-TSSOP 0 to 70

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