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SN75LVDS88B PDF预览

SN75LVDS88B

更新时间: 2024-11-19 22:53:31
品牌 Logo 应用领域
德州仪器 - TI 消费电路商用集成电路控制器
页数 文件大小 规格书
12页 152K
描述
TFT LCD PANEL TIMING CONTROLLER WITH LVDS INTERFACE

SN75LVDS88B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.89
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G100端子数量:100
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK电源:3.3 V
认证状态:Not Qualified子类别:Other Consumer ICs
表面贴装:YES技术:CMOS
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

SN75LVDS88B 数据手册

 浏览型号SN75LVDS88B的Datasheet PDF文件第2页浏览型号SN75LVDS88B的Datasheet PDF文件第3页浏览型号SN75LVDS88B的Datasheet PDF文件第4页浏览型号SN75LVDS88B的Datasheet PDF文件第5页浏览型号SN75LVDS88B的Datasheet PDF文件第6页浏览型号SN75LVDS88B的Datasheet PDF文件第7页 
SN75LVDS88B  
TFT LCD PANEL TIMING CONTROLLER  
WITH LVDS INTERFACE  
SLLS407 – FEBRUARY 2000  
Flatlink Interface Utilizes Low Power  
Differential Signalling(LVDS)  
Low Voltage CMOS 3.3 V Technology  
65 MHz Phase-Lock Input  
Suitable for Notebook Application  
XGA Resolution  
100-pin TQFP Package for Compact LCD  
Module  
Six Bit System Interface  
Tolerates 4 kV HBM ESD for LVDS Pins and  
2 kV HBM for Others  
Support Mainstream Data and Gate Drivers  
Optional Configurable Pins  
Improved Jitter Tolerance  
description  
The SN75LVDS88B(LVDS panel timing controller) integrates a Flatlink signal interface with a TFT LCD timing  
controller. It resides in the LCD panel and provides interface between the graphic controller and a TFT LCD  
panel.  
The SN75LVDS88B accepts host data through 3 pairs of inputs (18-bits) making up the LVDS bus, which is a  
low-EMI high-throughput interface. SN75LVDS88B then reformats the received image data into a specific data  
format and synchronous timing suitable for driving LCD panel column and row drivers. This device supports  
XGA resolution.  
The SN75LVDS88B is easily configured by several selection terminals and is equipped with default timing  
specifications to support mainstream gate and source drivers on the market.  
block diagram  
Data Alignment  
Source  
Data  
Format  
SYNC  
Flatlink  
(18-bit)  
Timing  
Signal  
CTRL  
Generator  
Interface  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Flatlink is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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