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SN75LVDS82DGG

更新时间： 2024-01-20 03:34:14
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德州仪器 - TI /
页数 文件大小 规格书
15页 203K
描述
FLATLINKE RECEIVER

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SN75LVDS82DGG 数据手册

 浏览型号SN75LVDS82DGG的Datasheet PDF文件第2页浏览型号SN75LVDS82DGG的Datasheet PDF文件第3页浏览型号SN75LVDS82DGG的Datasheet PDF文件第4页浏览型号SN75LVDS82DGG的Datasheet PDF文件第5页浏览型号SN75LVDS82DGG的Datasheet PDF文件第6页浏览型号SN75LVDS82DGG的Datasheet PDF文件第7页 
SN75LVDS82  
FLATLINK RECEIVER  
SLLS259D – NOVEMBER 1996 – REVISED MAY 1999  
DGG PACKAGE  
(TOP VIEW)  
4:28 Data Channel Expansion at up to 227.5  
Million Bytes per Second (Mbytes/s)  
Throughput  
D22  
D23  
V
CC  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
Suited for SVGA, XGA, or SXGA Display  
Data Transmission From Controller to  
Display With Very Low EMI  
D21  
D20  
D19  
GND  
D18  
D17  
D16  
2
D24  
3
GND  
4
4 Data Channels and Clock Low-Voltage  
Differential Channels In and 28 Data and  
Clock Low-Voltage TTL Channels Out  
D25  
5
D26  
6
D27  
7
Operates From a Single 3.3-V Supply With  
250 mW Typ  
LVDSGND  
A0M  
8
V
9
CC  
A0P  
D15  
D14  
10  
11  
5-V Tolerant SHTDN Input  
A1M  
Falling Clock-Edge-Triggered Outputs  
45 D13  
44 GND  
43 D12  
A1P 12  
LVDSV 13  
LVDSGND 14  
Packaged in Thin Shrink Small-Outline  
Package With 20-Mil Terminal Pitch  
CC  
Consumes Less Than 1 mW When Disabled  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
A2M  
A2P  
D11  
D10  
Wide Phase-Lock Input Frequency  
Range . . . 31 MHz to 68 MHz  
CLKINM  
CLKINP  
A3M  
V
CC  
No External Components Required for PLL  
D9  
D8  
D7  
GND  
D6  
D5  
D4  
D3  
Inputs Meet or Exceed the Requirements of  
the ANSI EIA/TIA-644 Standard  
A3P  
LVDSGND  
PLLGND  
Improved Replacement for the National  
DS90C582  
PLLV  
CC  
PLLGND  
SHTDN  
CLKOUT  
D0  
description  
The SN75LVDS82 FlatLink receiver contains  
four serial-in 7-bit parallel-out shift registers, a 7×  
clock synthesizer, and five low-voltage differential  
signaling (LVDS) line receivers in a single  
V
CC  
D2  
D1  
GND  
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the  
SN75LVDS81, over five balanced-pair conductors and expansion to 28 bits of single-ended low-voltage TTL  
(LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84  
or SN75LVDS85 for 21-bit transfers.  
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×)  
the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate.  
A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for  
the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).  
The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control.  
The data bus appears the same at the input to the transmitter and output of the receiver with the data  
transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear  
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A  
low-level on SHTDN clears all internal registers to a low level.  
The SN75LVDS82 is characterized for operation over ambient air temperatures of 0 C to 70 C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a registered trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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SN75LVDS82DGG 替代型号

型号 品牌 替代类型 描述 数据表
SN75LVDS82DGGG4 TI

类似代替

 FlatLink™ Receiver 56-TSSOP 0 to 70
SN75LVDS82DGGR TI

类似代替

 FlatLink™ RECEIVER

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SN75LVDS83AZQLR TI

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