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SN75LVDS82DGGR PDF预览

SN75LVDS82DGGR

更新时间： 2024-02-29 06:40:39
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德州仪器 - TI /
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FlatLink™ RECEIVER

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SN75LVDS82DGGR 数据手册

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SN75LVDS82  
www.ti.com  
SLLS259I –NOVEMBER 1996–REVISED APRIL 2011  
FlatLink™ RECEIVER  
Check for Samples: SN75LVDS82  
1
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
23  
•
4:28 Data Channel Expansion at up to  
238 Mbytes/s Throughput  
D22  
D23  
D24  
VCC  
D21  
D20  
D19  
GND  
D18  
D17  
D16  
VCC  
D15  
D14  
D13  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
•
Suited for SVGA, XGA, or SXGA Display  
Data Transmission From Controller to  
Display With Very Low EMI  
2
3
GND  
D25  
4
•
•
Four Data Channels and Clock Low-Voltage  
Differential Channels In and 28 Data and  
Clock Low-Voltage TTL Channels Out  
5
D26  
6
D27  
LVDSGND  
A0M  
7
Operates From a Single 3.3-V Supply With  
250 mW (Typ)  
8
9
•
•
•
5-V Tolerant SHTDN Input  
A0P  
10  
11  
12  
Falling Clock-Edge-Triggered Outputs  
A1M  
A1P  
Packaged in Thin Shrink Small-Outline  
Package (TSSOP) With 20-Mil Terminal Pitch  
LVDSVCC 13  
44 GND  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
LVDSGND  
A2M  
D12  
D11  
D10  
VCC  
D9  
•
•
Consumes Less Than 1 mW When Disabled  
Wide Phase-Lock Input Frequency  
Range . . . 31 MHz to 68 MHz  
A2P  
CLKINM  
CLKINP  
A3M  
•
•
No External Components Required for PLL  
Inputs Meet or Exceed the Requirements of  
ANSI EIA/TIA-644 Standard  
D8  
A3P  
D7  
GND  
D6  
•
Improved Replacement for the  
National™ DS90C582  
LVDSGND  
PLLGND  
PLLVCC  
PLLGND  
SHTDN  
CLKOUT  
D0  
D5  
D4  
DESCRIPTION  
The SN75LVDS82 FlatLink™ receiver contains four  
serial-in, 7-bit parallel-out shift registers, a 7× clock  
synthesizer, and five low-voltage differential signaling  
(LVDS) line receivers in a single integrated circuit.  
D3  
VCC  
D2  
GND  
D1  
These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81,  
over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL)  
synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or  
SN75LVDS85 for 21-bit transfers.  
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×)  
the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate.  
A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock  
for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
FlatLink is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1996–2011, Texas Instruments Incorporated  
1234567...18

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SN75LVDS82DGGR 替代型号

型号 品牌 替代类型 描述 数据表
SN75LVDS82DGGG4 TI

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