Not Recommended for New Designs
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢀ ꢇꢈ
ꢐ ꢑꢒꢁ ꢀꢓ ꢔ ꢐꢐ ꢕꢑ
ꢉ
ꢊ
ꢋ
ꢌꢄ
ꢍ
ꢎ
ꢏ
SLLS271I − MARCH 1997 − REVISED MAY 2009
DGG PACKAGE
(TOP VIEW)
D
D
4:28 Data Channel Compression at up to
238 MBytes/s Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
V
D4
1
56
55
54
53
52
51
50
49
48
47
46
CC
D5
D3
2
D6
D7
D2
3
D
D
D
D
D
D
28 Data Channels and Clock-In Low-Voltage
TTL
GND
D1
4
GND
D8
5
D0
6
4 Data Channels and Clock-Out
Low-Voltage Differential
D9
D27
LVDSGND
Y0M
Y0P
Y1M
7
D10
8
Operates From a Single 3.3-V Supply With
250 mW (Typ)
V
9
CC
D11
D12
10
11
ESD Protection Exceeds 6 kV
5-V Tolerant Data Inputs
45 Y1P
D13 12
GND 13
D14 14
Selectable Rising or Falling Edge-Triggered
Inputs
44 LVDSV
CC
43 LVDSGND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D15
D16
Y2M
D
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
Y2P
CLKSEL
D17
CLKOUTM
CLKOUTP
Y3M
D
Consumes Less Than 1 mW When Disabled
D
Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz
D18
D19
Y3P
D
D
D
No External Components Required for PLL
GND
D20
LVDSGND
PLLGND
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D21
PLLV
CC
Improved Replacement for the DS90C581
D22
PLLGND
SHTDN
CLKIN
D26
D23
description
V
CC
D24
D25
The SN75LVDS83 FlatLink transmitter contains
four 7-bit parallel-load serial-out shift registers, a
GND
7× clock synthesizer, and five low-voltage
differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of
single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors
for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit
links with the SN75LVDS86 receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL)
terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in
7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS
output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all
internal registers to a low level.
The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0_C to 70_C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a registered trademark of Texas Instruments.
ꢖꢑ ꢗ ꢆꢘ ꢙ ꢐꢔ ꢗ ꢁ ꢆ ꢒꢐꢒ ꢍꢎ ꢚ ꢛꢜ ꢝꢋ ꢌꢍꢛ ꢎ ꢍꢞ ꢟꢠ ꢜ ꢜ ꢡꢎꢌ ꢋꢞ ꢛꢚ ꢢꢠꢣ ꢊꢍꢟ ꢋꢌ ꢍꢛꢎ ꢤꢋ ꢌꢡ ꢥ
ꢖꢜ ꢛ ꢤꢠꢟ ꢌ ꢞ ꢟ ꢛꢎ ꢚꢛ ꢜ ꢝ ꢌ ꢛ ꢞ ꢢꢡ ꢟ ꢍꢚ ꢍꢟꢋ ꢌꢍ ꢛꢎꢞ ꢢꢡ ꢜ ꢌꢦ ꢡ ꢌꢡ ꢜ ꢝꢞ ꢛꢚ ꢐꢡꢧ ꢋꢞ ꢔꢎꢞ ꢌꢜ ꢠꢝ ꢡꢎꢌ ꢞ
ꢞ ꢌ ꢋ ꢎꢤ ꢋ ꢜꢤ ꢨ ꢋ ꢜꢜ ꢋ ꢎ ꢌꢩꢥ ꢖꢜ ꢛ ꢤꢠꢟ ꢌꢍꢛꢎ ꢢꢜ ꢛꢟ ꢡꢞ ꢞꢍ ꢎꢪ ꢤꢛꢡ ꢞ ꢎꢛꢌ ꢎꢡ ꢟꢡ ꢞꢞ ꢋꢜ ꢍꢊ ꢩ ꢍꢎꢟ ꢊꢠꢤ ꢡ
ꢌ ꢡ ꢞ ꢌꢍ ꢎꢪ ꢛꢚ ꢋ ꢊ ꢊ ꢢꢋ ꢜ ꢋ ꢝ ꢡ ꢌ ꢡ ꢜ ꢞ ꢥ
Copyright 1997 − 2009, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5秒后页面跳转
解析光耦仿真器：升级光耦合器技术的必要性
英伟达新一代Blackwell GPU过热问题致交付延迟
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
