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SN75LVDS83A PDF预览

SN75LVDS83A

更新时间: 2024-11-20 12:21:43
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德州仪器 - TI /
页数 文件大小 规格书
25页 781K
描述
FLATLINK™ TRANSMITTER

SN75LVDS83A 数据手册

 浏览型号SN75LVDS83A的Datasheet PDF文件第2页浏览型号SN75LVDS83A的Datasheet PDF文件第3页浏览型号SN75LVDS83A的Datasheet PDF文件第4页浏览型号SN75LVDS83A的Datasheet PDF文件第5页浏览型号SN75LVDS83A的Datasheet PDF文件第6页浏览型号SN75LVDS83A的Datasheet PDF文件第7页 
SN75LVDS83A  
www.ti.com  
SLLS980D JUNE 2009REVISED JUNE 2011  
FLATLINKTRANSMITTER  
Check for Samples: SN75LVDS83A  
Low-Voltage Differential  
Consumes Less Than 1mW When Disabled  
Selectable Rising or Falling Clock Edge  
Triggered Inputs  
ESD: 5kV HBM  
Support Spread Spectrum Clocking (SSC)  
Compatible with all OMAP2x, OMAP3x,  
and DaVinciApplication Processors  
1
FEATURES  
2
LVDS Display Serdes Interfaces Directly to  
LCD Display Panels with Integrated LVDS  
Package Options: 8.1mm x 14mm TSSOP  
3.3V Tolerant Data Inputs  
Transfer Rate up to 100Mpps (Mega Pixel Per  
Second); Pixel Clock Frequency Range 10MHz  
to 100MHz  
Suited for Display Resolutions Ranging From  
HVGA up to HD With Low EMI  
Operates From a Single 3.3V Supply and  
170mW (typ.) at 75MHz  
28 Data Channels Plus Clock In Low-Voltage  
TTL to 4 Data Channels Plus Clock Out  
APPLICATIONS  
LCD Display Panel Driver  
UMPC and Netbook PC  
Digital Picture Frame  
DESCRIPTION  
The SN75LVDS83A FlatLinktransmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock  
synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These  
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair  
conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS  
receiver.  
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock  
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The  
frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and  
serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.  
The frequency of CLKOUT is the same as the input clock, CLKIN.  
Application  
processor  
SN75LVDS83A  
FlatLinkTM Transmitter  
(e.g. OMAPTM  
)
TSSOP: 8 x 14mm DGG  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 20092011, Texas Instruments Incorporated  
 

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