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SN75LVDS83DGGR PDF预览

SN75LVDS83DGGR

更新时间： 2024-11-24 13:13:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
15页 206K
描述
FlatLink™ Transmitter 56-TSSOP 0 to 70

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中文翻译

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SN75LVDS83DGGR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Not Recommended零件包装代码：TSSOP
包装说明：TSSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：6.94Is Samacsys：N
差分输出：YES驱动器位数：4
高电平输入电流最大值：0.000025 A输入特性：STANDARD
接口集成电路类型：LINE DRIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：14 mm湿度敏感等级：2
功能数量：1端子数量：56
最高工作温度：70 °C最低工作温度：
输出特性：TOTEM-POLE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：110 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

SN75LVDS83DGGR 数据手册

 浏览型号SN75LVDS83DGGR的Datasheet PDF文件第2页浏览型号SN75LVDS83DGGR的Datasheet PDF文件第3页浏览型号SN75LVDS83DGGR的Datasheet PDF文件第4页浏览型号SN75LVDS83DGGR的Datasheet PDF文件第5页浏览型号SN75LVDS83DGGR的Datasheet PDF文件第6页浏览型号SN75LVDS83DGGR的Datasheet PDF文件第7页 
SN75LVDS83  
FLATLINK TRANSMITTER  
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999  
DGG PACKAGE  
(TOP VIEW)  
28:4 Data Channel Compression at up to  
227.5 Million Bytes per Second Throughput  
Suited for SVGA, XGA, or SXGA Display  
Data Transmission From Controller to  
Display With Very Low EMI  
V
D4  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
CC  
D5  
D3  
2
D6  
D7  
D2  
3
28 Data Channels and Clock-In Low-Voltage  
TTL  
GND  
D1  
4
GND  
D8  
5
D0  
6
4 Data Channels and Clock-Out  
Low-Voltage Differential  
D9  
D27  
LVDSGND  
Y0M  
Y0P  
Y1M  
7
D10  
8
Operates From a Single 3.3-V Supply With  
250 mW (Typ)  
V
9
CC  
D11  
D12  
10  
11  
ESD Protection Exceeds 6 kV  
5-V Tolerant Data Inputs  
D13 12  
GND 13  
D14 14  
45 Y1P  
Selectable Rising or Falling Edge-Triggered  
Inputs  
44 LVDSV  
CC  
43 LVDSGND  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
D15  
D16  
Y2M  
Packaged in Thin Shrink Small-Outline  
Package With 20-Mil Terminal Pitch  
Y2P  
CLKSEL  
D17  
CLKOUTM  
CLKOUTP  
Y3M  
Consumes Less Than 1 mW When Disabled  
Wide Phase-Lock Input Frequency  
Range . . . 31 MHz to 68 MHz  
D18  
D19  
Y3P  
No External Components Required for PLL  
GND  
D20  
LVDSGND  
PLLGND  
Outputs Meet or Exceed the Requirements  
of ANSI EIA/TIA-644 Standard  
D21  
PLLV  
CC  
Improved Replacement for the DS90C581  
D22  
PLLGND  
SHTDN  
CLKIN  
D26  
D23  
description  
V
CC  
D24  
D25  
The SN75LVDS83 FlatLink transmitter contains  
four 7-bit parallel-load serial-out shift registers, a  
7× clock synthesizer, and five low-voltage  
GND  
differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of  
single-endedlow-voltageTTL(LVTTL)datatobesynchronouslytransmittedoverfivebalanced-pairconductors  
for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit  
links with the SN75LVDS86 receiver.  
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock  
signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL)  
terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in  
7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS  
output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.  
The SN75LVDS83 requires no external components and little or no control. The data bus appears the same  
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The  
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock  
and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all  
internal registers to a low level.  
The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0 C to 70 C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a registered trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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SN75LVDS83DGGR 替代型号

型号 品牌 替代类型 描述 数据表
SN75LVDS83DGGG4 TI

完全替代

 FlatLink TRANSMITTER
SN75LVDS83DGG TI

完全替代

 FLATLINKE TRANSMITTER

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