Datasheet > SN75LVDS83B_17

SN75LVDS83B_17

更新时间： 2024-11-21 02:58:35

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
28页	855K
描述
FlatLink Transmitter

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数据手册

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SN75LVDS83B_17 数据手册

SN75LVDS83B

www.ti.com ........................................................................................................................................................................................................ SLLS846–MAY 2009

FLATLINK™ TRANSMITTER

FEATURES

•

28 Data Channels Plus Clock In Low-Voltage

TTL to 4 Data Channels Plus Clock Out

Low-Voltage Differential

•

LVDS Display Serdes Interfaces Directly to

LCD Display Panels with Integrated LVDS

•

Consumes Less Than 1mW When Disabled

•

Package Options: 4.5mm x 7mm BGA, and

8.1mm x 14mm TSSOP

Selectable Rising or Falling Clock Edge

Triggered Inputs

1.8V up to 3.3V Tolerant Data Inputs to

Connect Directly to Low-Power, Low-Voltage

Application and Graphic Processors

•

ESD: 5kV HBM

Support Spread Spectrum Clocking (SSC)

•

Transfer Rate up to 135Mpps (Mega Pixel Per

Second); Pixel Clock Frequency Range 10MHz

to 135MHz

Compatible with all OMAP™2x, OMAP™3x,

and DaVinci™ Application Processors

•

Suited for Display Resolutions Ranging From

HVGA up to HD With Low EMI

APPLICATIONS

•

LCD Display Panel Driver

UMPC and Netbook PC

Digital Picture Frame

Operates From a Single 3.3V Supply and

170mW (typ.) at 75MHz

DESCRIPTION

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock

synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair

conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS

receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock

signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The

frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and

serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.

The frequency of CLKOUT is the same as the input clock, CLKIN.

Application

processor

SN75LVDS83B

FlatLink^TMTransmitter

(e.g. OMAP^TM

)

Package Options

TSSOP: 8 x 14mm DGG

BGA: 4.5 x 7mm

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...28

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