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SN74AUP1G98YEPR

更新时间： 2024-09-13 03:13:47
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路栅
页数 文件大小 规格书
16页 315K
描述
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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中文翻译

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SN74AUP1G98YEPR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：DSBGA-6
针数：6Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.26Is Samacsys：N
系列：AUP/ULP/VJESD-30 代码：R-PBGA-B6
长度：1.4 mm负载电容（CL）：30 pF
逻辑集成电路类型：LOGIC CIRCUIT最大I（ol）：0.0017 A
功能数量：1端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA6,2X3,20
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.2/3.3 VProp。Delay @ Nom-Sup：26.8 ns
认证状态：Not Qualified施密特触发器：YES
座面最大高度：0.5 mm子类别：Gates
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：0.9 mmBase Number Matches：1

SN74AUP1G98YEPR 数据手册

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SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004  
D
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Low Static-Power Consumption;  
D
Optimized for 3.3-V Operation  
D
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
I
= 0.9 µA Max  
CC  
D
D
D
D
t
= 5.3 ns Max at 3.3 V  
pd  
Low Dynamic-Power Consumption;  
= 4.6 pF Typ at 3.3 V  
Suitable for Point-to-Point Applications  
C
pd  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
Low Input Capacitance; C = 1.5 pF Typ  
i
D
Low Noise − Overshoot and Undershoot  
<10% of V  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
CC  
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
Includes Schmitt-Trigger Inputs  
D
ESD Protection Exceeds 5000 V With  
Human-Body Model  
D
Wide Operating V  
Range of 0.8 V to 3.6 V  
CC  
DBV OR DCK PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3 4  
2 5  
1 6  
A
GND  
B
Y
V
C
1
2
3
6
5
4
B
GND  
A
C
V
Y
CC  
CC  
description/ordering information  
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire V  
CC  
range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent  
signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
Switching Characteristics  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
†
at 25 MHz  
(µA)  
3.5  
3
100%  
100%  
80%  
60%  
80%  
2.5  
2
Input  
Output  
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
1.5  
1
†
Logic  
40%  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
−0.5  
10  
15 20  
Time − ns  
AUP1G08 data at C = 15 pF  
0
5
25  
35 40 45  
30  
†
Single, dual, and triple gates  
†
L
Figure 2. Excellent Signal Integrity  
Figure 1. AUP − The Lowest-Power Family  
The SN74AUP1G98 features configurable multiple functions. The output state is determined by eight patterns  
of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter.  
All inputs can be connected to V  
or GND.  
CC  
The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition  
and better switching-noise immunity at the input.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

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SN74AUP1G98YEPR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1G98YZPR TI

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