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SN74AUP1G99_09

更新时间： 2024-10-31 11:52:03
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LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS

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SN74AUP1G99  
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES594C–JULY 2004–REVISED DECEMBER 2007  
1
FEATURES  
2
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
•
•
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 5 pF Typ at 3.3 V)  
•
•
•
tpd = 7.4 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (CI = 1.5 pF)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
•
Input-Disable Feature Allows Floating Input  
Conditions  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
Includes Schmitt-Trigger Inputs  
YZP PACKAGE  
(BOTTOM VIEW)  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
4 5  
C
D
Y
GND  
B
A
OE  
OE  
A
B
VCC  
Y
D
1
2
3
4
8
7
6
5
3 6  
1
2
8
7
OE  
A
VCC  
Y
2
7
1 8  
V
CC  
GND  
C
3
4
6
5
B
D
C
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
xxxxxx  
Switching Characteristics  
†
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
100%  
at 25 MHz  
3.5  
3
(µA)  
100%  
80%  
2.5  
2
80%  
Input  
Output  
60%  
40%  
1.5  
1
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
†
Logic  
0.5  
0
20%  
0%  
20%  
0%  
−0.5  
AUP  
AUP  
20  
Time − ns  
10  
15  
0
5
25  
35 40  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 1. AUP - The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2007, Texas Instruments Incorporated  
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