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SN74AUP1G99DCTRG4 PDF预览

SN74AUP1G99DCTRG4

更新时间： 2024-09-13 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路光电二极管输出元件栅
页数 文件大小 规格书
24页 629K
描述
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS

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SN74AUP1G99DCTRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：LSSOP, SSOP8,.16针数：8
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.66系列：AUP/ULP/V
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：2.95 mm负载电容（CL）：30 pF
逻辑集成电路类型：LOGIC CIRCUIT最大I（ol）：0.0017 A
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：SSOP8,.16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：1.2/3.3 V
Prop。Delay @ Nom-Sup：36.1 ns认证状态：Not Qualified
施密特触发器：YES座面最大高度：1.3 mm
子类别：Gates最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.1 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：2.8 mmBase Number Matches：1

SN74AUP1G99DCTRG4 数据手册

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SN74AUP1G99  
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES594C–JULY 2004–REVISED DECEMBER 2007  
1
FEATURES  
2
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
•
•
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 5 pF Typ at 3.3 V)  
•
•
•
tpd = 7.4 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (CI = 1.5 pF)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
•
Input-Disable Feature Allows Floating Input  
Conditions  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
Includes Schmitt-Trigger Inputs  
YZP PACKAGE  
(BOTTOM VIEW)  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
4 5  
C
D
Y
GND  
B
A
OE  
OE  
A
B
VCC  
Y
D
1
2
3
4
8
7
6
5
3 6  
1
2
8
7
OE  
A
VCC  
Y
2
7
1 8  
V
CC  
GND  
C
3
4
6
5
B
D
C
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
xxxxxx  
Switching Characteristics  
†
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
100%  
at 25 MHz  
3.5  
3
(µA)  
100%  
80%  
2.5  
2
80%  
Input  
Output  
60%  
40%  
1.5  
1
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
†
Logic  
0.5  
0
20%  
0%  
20%  
0%  
−0.5  
AUP  
AUP  
20  
Time − ns  
10  
15  
0
5
25  
35 40  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 1. AUP - The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2007, Texas Instruments Incorporated  
1234567...24

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