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SN74AUP1T14DCKR

更新时间： 2024-11-01 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 输出元件输入元件
页数 文件大小 规格书
11页 163K
描述
LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER INVERTER GATE

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SN74AUP1T14DCKR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：TSSOP, TSSOP5/6,.08针数：5
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.71系列：AUP/ULP/V
JESD-30 代码：R-PDSO-G5JESD-609代码：e4
长度：2 mm负载电容（CL）：30 pF
逻辑集成电路类型：INVERTER最大I（ol）：0.004 A
湿度敏感等级：1位数：1
功能数量：1输入次数：1
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP5/6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：2.5/3.3 V最大电源电流（ICC）：0.0009 mA
Prop。Delay @ Nom-Sup：10 ns传播延迟（tpd）：10.8 ns
认证状态：Not Qualified施密特触发器：YES
座面最大高度：1.1 mm子类别：Gates
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.25 mm
Base Number Matches：1

SN74AUP1T14DCKR 数据手册

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SN74AUP1T14  
www.ti.com  
SCES802 –APRIL 2010  
LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE  
SCHMITT-TRIGGER INVERTER GATE  
Check for Samples: SN74AUP1T14  
1
FEATURES  
•
Single-Supply Voltage Translator  
•
•
More Gate Options Available at  
www.ti.com/littlelogic  
•
Output Level Up to Supply VCC CMOS Level  
ESD Performance Tested Per JESD 22  
–
–
–
–
1.8 V to 3.3 V (at VCC = 3.3 V)  
2.5 V to 3.3 V (at VCC = 3.3 V)  
1.8 V to 2.5 V (at VCC = 2.5 V)  
3.3 V to 2.5 V (at VCC = 2.5 V  
–
2000-V Human-Body Model  
(A114-B, Class II)  
–
1000-V Charged-Device Model (C101)  
•
Schmitt-Trigger Inputs Reject Input Noise and  
Provide Better Output Signal Integrity  
DCK PACKAGE  
(TOP VIEW)  
•
•
Ioff Supports Partial Power Down (VCC = 0 V)  
1
2
3
5
4
VCC  
NC  
A
Very Low Static Power Consumption:  
0.1 µA  
•
•
•
Very Low Dynamic Power Consumption:  
0.9 µA  
GND  
Y
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Pb-Free Packages Available: SC-70 (DCK)  
2 x 2.1 x 0.65 mm (Height 1.1 mm)  
DESCRIPTION/ORDERING INFORMATION  
The SN74AUP1T14 performs the Boolean function Y = A with designation for logic-level translation applications  
with output referenced to supply VCC  
.
AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in  
operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V  
VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).  
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external  
controllers or processors.  
Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise  
immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger  
inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.  
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile  
applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of  
the device. No damage occurs to the device under these conditions.  
The SN74AUP1T14 is designed with optimized current-drive capability of 4 mA to reduce line reflections,  
overshoot, and undershoot caused by high-drive outputs.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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与SN74AUP1T14DCKR相关器件

型号 品牌 获取价格 描述 数据表
SN74AUP1T14DCKT TI

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 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER INVERTER GATE
SN74AUP1T157 TI

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 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER M
SN74AUP1T157DCKR TI

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 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER M
SN74AUP1T157DCKT TI

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 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER M
SN74AUP1T158 TI

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 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER M
SN74AUP1T158DCKR TI

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 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER M
SN74AUP1T158DCKT TI

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 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER M
SN74AUP1T17 TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER BUFFER GATE
SN74AUP1T17_15 TI

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 		3.3-V CMOS Output Single Schmitt-Trigger Buffer Gate
SN74AUP1T17DCKR TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER BUFFER GATE

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