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SN74AUP1T57DBVRE4

更新时间： 2024-11-06 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
24页 932K
描述
SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS

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SN74AUP1T57DBVRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOT-23
包装说明：GREEN, PLASTIC, SOT-23, 6 PIN针数：6
Reach Compliance Code：unknown风险等级：5.09
Is Samacsys：N接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G6JESD-609代码：e4
长度：2.9 mm湿度敏感等级：1
功能数量：1端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：TSOP6,.11,37封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：1.2/3.3 V认证状态：Not Qualified
座面最大高度：1.45 mm子类别：Other Interface ICs
最大供电电压：3.6 V最小供电电压：2.3 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.95 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.6 mm
Base Number Matches：1

SN74AUP1T57DBVRE4 数据手册

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SN74AUP1T57  
www.ti.com  
SCES611G –OCTOBER 2004–REVISED MAY 2010  
SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR  
WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS  
Check for Samples: SN74AUP1T57  
1
FEATURES  
DBV OR DCK PACKAGE  
2
•
Available in the Texas Instruments NanoStar™  
(TOP VIEW)  
Packages  
1
2
3
6
5
4
B
GND  
A
C
•
•
•
•
•
•
•
Single-Supply Voltage Translator  
1.8 V to 3.3 V (at VCC = 3.3 V)  
2.5 V to 3.3 V (at VCC = 3.3 V)  
1.8 V to 2.5 V (at VCC = 2.5 V)  
3.3 V to 2.5 V (at VCC = 2.5 V)  
Nine Configurable Gate Logic Functions  
VCC  
Y
DRY OR DSF PACKAGE  
(TOP VIEW)  
1
2
3
6
5
4
B
GND  
A
C
Schmitt-Trigger Inputs Reject Input Noise and  
Provide Better Output Signal Integrity  
VCC  
Y
•
•
•
Ioff Supports Partial-Power-Down Mode With  
Low Leakage Current (0.5 mA)  
Very Low Static and Dynamic Power  
Consumption  
YFP OR YZP PACKAGE  
(TOP VIEW)  
Pb-Free Packages Available: SON (DRY or  
DSF), SOT-23 (DBV), SC-70 (DCK), and  
NanoStar WCSP  
A1  
B1  
C1  
A2  
B2  
C2  
1
2
3
6
5
4
B
GND  
A
C
VCC  
Y
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Performance Tested Per JESD 22  
–
2000-V Human-Body Model  
(A114-B, Class II)  
–
1000-V Charged-Device Model (C101)  
•
Related Devices: SN74AUP1T58,  
SN74AUP1T97, and SN74AUP1T98  
DESCRIPTION/ORDERING INFORMATION  
AUP technology is the industry's lowest-power logic technology designed for use in battery-operated or battery  
backed-up equipment. The SN74AUP1T57 is designed for logic-level translation applications with input switching  
levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply.  
The wide VCC range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and  
ensures normal operation between this range.  
Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise  
immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger  
inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.  
The SN74AUP1T57 can be easily configured to perform a required gate function by connecting A, B, and C  
inputs to VCC or ground (see Function Selection table). Up to nine commonly used logic gate functions can be  
performed.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoStar is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2010, Texas Instruments Incorporated  
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SN74AUP1T57DBVRE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1T57DBVTG4 TI

完全替代

 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS
SN74AUP1T57DBVR TI

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