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SN74AUP1T58YFPR

更新时间： 2024-11-06 09:15:11
品牌 Logo 应用领域
德州仪器 - TI 转换器电平转换器驱动程序和接口接口集成电路PC
页数 文件大小 规格书
24页 922K
描述
SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE FUNCTIONS

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SN74AUP1T58YFPR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA6,2X3,16针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.56Samacsys Confidence：
Samacsys Status：ReleasedSamacsys PartID：606906
Samacsys Pin Count：6Samacsys Part Category：Integrated Circuit
Samacsys Package Category：OtherSamacsys Footprint Name：BGA6C40P2X3_117X77X50
Samacsys Released Date：2017-01-12 12:59:53Is Samacsys：N
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：R-XBGA-B6
JESD-609代码：e1长度：1.4 mm
湿度敏感等级：1位数：1
功能数量：1端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：PUSH-PULL封装主体材料：UNSPECIFIED
封装代码：VFBGA封装等效代码：BGA6,2X3,16
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：0.5 mm
子类别：Other Interface ICs最大压摆率：0.0009 mA
最大供电电压：3.6 V最小供电电压：2.3 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.9 mm
Base Number Matches：1

SN74AUP1T58YFPR 数据手册

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SN74AUP1T58  
www.ti.com  
SCES612H –OCTOBER 2004–REVISED MARCH 2010  
SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR  
WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS  
Check for Samples: SN74AUP1T58  
1
FEATURES  
DBV OR DCK PACKAGE  
2
•
Available in the Texas Instruments NanoStar™  
(TOP VIEW)  
Packages  
1
2
3
6
5
4
B
GND  
A
C
•
•
•
•
•
•
•
Single-Supply Voltage Translator  
1.8 V to 3.3 V (at VCC = 3.3 V)  
2.5 V to 3.3 V (at VCC = 3.3 V)  
1.8 V to 2.5 V (at VCC = 2.5 V)  
3.3 V to 2.5 V (at VCC = 2.5 V  
Nine Configurable Gate Logic Functions  
VCC  
Y
DRY OR DSF PACKAGE  
(TOP VIEW)  
1
2
3
6
5
4
B
GND  
A
C
Schmitt-Trigger Inputs Reject Input Noise and  
Provide Better Output Signal Integrity  
VCC  
Y
•
•
•
Ioff Supports Partial-Power-Down Mode With  
Low Leakage Current (0.5 mA)  
Very Low Static and Dynamic Power  
Consumption  
YFP OR YZP PACKAGE  
(TOP VIEW)  
Pb-Free Packages Available: SON (DRY or  
DSF), SOT-23 (DBV), SC-70 (DCK), and  
NanoStar WCSP  
A1  
B1  
C1  
A2  
B2  
C2  
1
2
3
6
5
4
B
GND  
A
C
VCC  
Y
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Performance Tested Per JESD 22  
–
2000-V Human-Body Model  
(A114-B, Class II)  
–
1000-V Charged-Device Model (C101)  
•
Related Devices: SN74AUP1T57,  
SN74AUP1T97, and SN74AUP1T98  
DESCRIPTION/ORDERING INFORMATION  
AUP technology is the industry's lowest-power logic technology designed for use in battery-operated or battery  
backed-up equipment. The SN74AUP1T58 is designed for logic-level translation applications with input switching  
levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply.  
The wide VCC range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and  
ensures normal operation between this range.  
Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise  
immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger  
inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.  
The SN74AUP1T58 can be easily configured to perform a required gate function by connecting A, B, and C  
inputs to VCC or ground (see Function Selection table). Up to nine commonly used logic gate functions can be  
performed.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoStar is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2010, Texas Instruments Incorporated  
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