5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 其他逻辑集成电路> SN74AUP1G99DCUTE4
SN74AUP1G99DCUTE4 PDF预览

SN74AUP1G99DCUTE4

更新时间： 2024-11-05 11:49:31
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路光电二极管输出元件栅
页数 文件大小 规格书
24页 629K
描述
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74AUP1G99DCUTE4 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：VSSOP, TSSOP8,.12,20针数：8
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.15Is Samacsys：N
系列：AUP/ULP/VJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：2.3 mm
负载电容（CL）：30 pF逻辑集成电路类型：LOGIC CIRCUIT
最大I（ol）：0.0017 A湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VSSOP封装等效代码：TSSOP8,.12,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：1.2/3.3 VProp。Delay @ Nom-Sup：36.1 ns
认证状态：Not Qualified施密特触发器：YES
座面最大高度：0.9 mm子类别：Gates
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.1 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：2 mm
Base Number Matches：1

SN74AUP1G99DCUTE4 数据手册

 浏览型号SN74AUP1G99DCUTE4的Datasheet PDF文件第2页浏览型号SN74AUP1G99DCUTE4的Datasheet PDF文件第3页浏览型号SN74AUP1G99DCUTE4的Datasheet PDF文件第4页浏览型号SN74AUP1G99DCUTE4的Datasheet PDF文件第5页浏览型号SN74AUP1G99DCUTE4的Datasheet PDF文件第6页浏览型号SN74AUP1G99DCUTE4的Datasheet PDF文件第7页 
SN74AUP1G99  
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES594C–JULY 2004–REVISED DECEMBER 2007  
1
FEATURES  
2
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
•
•
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 5 pF Typ at 3.3 V)  
•
•
•
tpd = 7.4 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (CI = 1.5 pF)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
•
Input-Disable Feature Allows Floating Input  
Conditions  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
Includes Schmitt-Trigger Inputs  
YZP PACKAGE  
(BOTTOM VIEW)  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
4 5  
C
D
Y
GND  
B
A
OE  
OE  
A
B
VCC  
Y
D
1
2
3
4
8
7
6
5
3 6  
1
2
8
7
OE  
A
VCC  
Y
2
7
1 8  
V
CC  
GND  
C
3
4
6
5
B
D
C
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
xxxxxx  
Switching Characteristics  
†
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
100%  
at 25 MHz  
3.5  
3
(µA)  
100%  
80%  
2.5  
2
80%  
Input  
Output  
60%  
40%  
1.5  
1
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
†
Logic  
0.5  
0
20%  
0%  
20%  
0%  
−0.5  
AUP  
AUP  
20  
Time − ns  
10  
15  
0
5
25  
35 40  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 1. AUP - The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2007, Texas Instruments Incorporated  
1234567...24

中文翻译

下载PDF

SN74AUP1G99DCUTE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1G99DCURE4 TI

完全替代

 LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS
SN74AUP1G99DCUT TI

完全替代

 LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS
SN74AUP1G99DCUR TI

完全替代

 LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS

与SN74AUP1G99DCUTE4相关器件

型号 品牌 获取价格 描述 数据表
SN74AUP1G99DCUTG4 TI

获取价格

 		LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS
SN74AUP1G99YEPR TI

获取价格

 		LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS
SN74AUP1G99YZPR TI

获取价格

 		LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS
SN74AUP1T00 TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1T00DCKR TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1T00DCKT TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1T02 TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT,SINGLE 2-INPUT POSITIVE-NOR GATE
SN74AUP1T02DCKR TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT,SINGLE 2-INPUT POSITIVE-NOR GATE
SN74AUP1T02DCKT TI

获取价格

 		LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT,SINGLE 2-INPUT POSITIVE-NOR GATE
SN74AUP1T04 TI

获取价格

 		LOW POWER,1.8/2.5/3.3-V INPUT,3.3-V COMS OUTPUT, SINGLE INVERTER GATE

与SN74AUP1G99DCUTE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证