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SN74AUC2G125_09

更新时间： 2024-11-24 11:51:07
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德州仪器 - TI 输出元件
页数 文件大小 规格书
14页 552K
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DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74AUC2G125_09 数据手册

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SN74AUC2G125  
DUAL BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES532D–DECEMBER 2003–REVISED AUGUST 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Low Power Consumption, 10 μA at 1.8 V  
±8-mA Output Drive at 1.8 V  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 1.8 ns at 1.8 V  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
2A  
4 5  
GND  
VCC  
1OE  
1
2
3
4
8
7
6
5
VCC  
1OE  
1A  
1
2
8
7
3 6  
1Y  
2Y  
1A  
1A  
2Y  
2OE  
1Y  
2
7
2OE  
VCC  
2OE  
1 8  
1OE  
GND  
2A  
3
4
6
5
2Y  
1Y  
2A  
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V  
VCC operation.  
The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the  
associated output-enable (OE) input is high.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(3)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Reel of 3000  
SN74AUC2G125YZPR  
_ _ _UM_  
–40°C to 85°C  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
SN74AUC2G125DCTR  
SN74AUC2G125DCUR  
U25_ _ _  
U25_  
VSSOP – DCU  
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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