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SN74AUC2G125YZPR PDF预览

SN74AUC2G125YZPR

更新时间： 2024-11-15 22:49:31
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
12页 261K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74AUC2G125YZPR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：DSBGA-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.54Is Samacsys：N
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：AUCJESD-30 代码：R-XBGA-B8
JESD-609代码：e1长度：1.9 mm
负载电容（CL）：15 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A湿度敏感等级：1
位数：1功能数量：2
端口数量：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：UNSPECIFIED封装代码：VFBGA
封装等效代码：BGA8,2X4,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：1.2/2.5 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：3.6 ns
传播延迟（tpd）：3.6 ns认证状态：Not Qualified
座面最大高度：0.5 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：0.9 mmBase Number Matches：1

SN74AUC2G125YZPR 数据手册

 浏览型号SN74AUC2G125YZPR的Datasheet PDF文件第2页浏览型号SN74AUC2G125YZPR的Datasheet PDF文件第3页浏览型号SN74AUC2G125YZPR的Datasheet PDF文件第4页浏览型号SN74AUC2G125YZPR的Datasheet PDF文件第5页浏览型号SN74AUC2G125YZPR的Datasheet PDF文件第6页浏览型号SN74AUC2G125YZPR的Datasheet PDF文件第7页 
SN74AUC2G125  
DUAL BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES532A–DECEMBER 2003–REVISED MARCH 2005  
FEATURES  
DCT OR DCU PACKAGE  
(TOP VIEW)  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
1
2
3
4
8
7
6
5
1OE  
1A  
2Y  
V
CC  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
2OE  
1Y  
2A  
GND  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
•
Sub-1-V Operable  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Max tpd of 1.8 ns at 1.8 V  
Low Power Consumption, 10 µA at 1.8 V  
±8-mA Output Drive at 1.8 V  
4
3
2
1
5
6
7
8
GND  
2Y  
2A  
1Y  
1A  
1OE  
2OE  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V  
VCC operation.  
The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the  
associated output-enable (OE) input is high.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of  
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
Tape and reel SN74AUC2G125YEPR  
_ _ _UM_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Tape and reel SN74AUC2G125YZPR  
–40°C to 85°C  
SSOP – DCT  
Tape and reel SN74AUC2G125DCTR  
Tape and reel SN74AUC2G125DCUR  
U25_ _ _  
UM_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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SN74AUC2G125YZPR 替代型号

型号 品牌 替代类型 描述 数据表
74AUC2G126DCURG4 TI

完全替代

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC2G125DCUR TI

完全替代

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC2G126YZPR TI

类似代替

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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