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SN74AUC125RGYR PDF预览

SN74AUC125RGYR

更新时间： 2024-11-20 09:15:27
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
9页 168K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74AUC125RGYR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC14/18,.14SQ,20针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.39控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：AUC
JESD-30 代码：S-PQCC-N14JESD-609代码：e4
长度：3.5 mm负载电容（CL）：15 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.009 A
湿度敏感等级：2位数：1
功能数量：4端口数量：2
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC14/18,.14SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/2.5 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：3.7 ns传播延迟（tpd）：3.7 ns
认证状态：Not Qualified座面最大高度：1 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：3.5 mm
Base Number Matches：1

SN74AUC125RGYR 数据手册

 浏览型号SN74AUC125RGYR的Datasheet PDF文件第2页浏览型号SN74AUC125RGYR的Datasheet PDF文件第3页浏览型号SN74AUC125RGYR的Datasheet PDF文件第4页浏览型号SN74AUC125RGYR的Datasheet PDF文件第5页浏览型号SN74AUC125RGYR的Datasheet PDF文件第6页浏览型号SN74AUC125RGYR的Datasheet PDF文件第7页 
SN74AUC125  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES508A–NOVEMBER 2003–REVISED MARCH 2005  
FEATURES  
RGY PACKAGE  
(TOP VIEW)  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
1
14  
1A  
1Y  
13  
12  
11  
10  
9
2
3
4
5
6
4OE  
4A  
•
•
•
•
•
Sub-1-V Operable  
2OE  
2A  
2Y  
4Y  
3OE  
3A  
Max tpd of 2.1 ns at 1.8 V  
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
7
8
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1500-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCC operation, but is designed specifically for 1.6-V  
to 1.95-V VCC operation.  
The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–40°C to 85°C  
QFN – RGY  
Tape and reel  
SN74AUC125RGYR  
MS125  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
L
A
H
L
H
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...9

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SN74AUC125RGYR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC125RGYRG4 TI

完全替代

 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC126RGYRG4 TI

完全替代

 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC126RGYR TI

完全替代

 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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