5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74AUC16374
SN74AUC16374 PDF预览

SN74AUC16374

更新时间： 2024-11-19 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
12页 296K
描述
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74AUC16374 数据手册

 浏览型号SN74AUC16374的Datasheet PDF文件第2页浏览型号SN74AUC16374的Datasheet PDF文件第3页浏览型号SN74AUC16374的Datasheet PDF文件第4页浏览型号SN74AUC16374的Datasheet PDF文件第5页浏览型号SN74AUC16374的Datasheet PDF文件第6页浏览型号SN74AUC16374的Datasheet PDF文件第7页 
SN74AUC16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES403D–JULY 2002–REVISED JUNE 2005  
FEATURES  
DGG OR DGV PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
2
3
4
•
Ioff Supports Partial-Power-Down Mode  
Operation  
5
6
•
•
•
•
•
Sub-1-V Operable  
V
CC  
7
V
CC  
Max tpd of 2 ns at 1.8 V  
8
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
Low Power Consumption, 20-µA Max ICC  
±8-mA Output Drive at 1.8 V  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
V
CC  
V
CC  
DESCRIPTION/ORDERING INFORMATION  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
This 16-bit edge-triggered D-type flip-flop is  
operational at 0.8-V to 2.7-V VCC, but is designed  
specifically for 1.65-V to 1.95-V VCC operation.  
The SN74AUC16374 is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers. It can be used as  
two 8-bit flip-flops or one 16-bit flip-flop. On the  
positive transition of the clock (CLK) input, the Q  
outputs of the flip-flop take on the logic levels set up  
at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74AUC16374DGGR  
TOP-SIDE MARKING  
AUC16374  
TSSOP – DGG  
TVSOP – DGV  
VFBGA – GQL(2)  
Tape and reel  
–40°C to 85°C  
Tape and reel  
Tape and reel  
SN74AUC16374DGVR  
SN74AUC16374GQLR  
MH374  
MH374  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) Package preview  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2002–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...12

中文翻译

下载PDF

与SN74AUC16374相关器件

型号 品牌 获取价格 描述 数据表
SN74AUC16374_14 TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374DGGR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374DGVR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374GQLR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374ZQLR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16501 TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC16501DGG TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC16501DGGR TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC16501DGV TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC16501DGVR TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

与SN74AUC16374相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证