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SN74AUC16244GQLR PDF预览

SN74AUC16244GQLR

更新时间： 2024-11-19 22:16:03
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
12页 314K
描述
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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SN74AUC16244GQLR 数据手册

 浏览型号SN74AUC16244GQLR的Datasheet PDF文件第2页浏览型号SN74AUC16244GQLR的Datasheet PDF文件第3页浏览型号SN74AUC16244GQLR的Datasheet PDF文件第4页浏览型号SN74AUC16244GQLR的Datasheet PDF文件第5页浏览型号SN74AUC16244GQLR的Datasheet PDF文件第6页浏览型号SN74AUC16244GQLR的Datasheet PDF文件第7页 
SN74AUC16244  
16-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
SCES399D – JULY 2002 – REVISED JANUARY 2003  
DGG OR DGV PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
2OE  
1
2
3
4
5
6
7
8
9
48  
47 1A1  
46 1A2  
45 GND  
44 1A3  
43 1A4  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Sub 1-V Operable  
V
42  
V
Max t of 2 ns at 1.8 V  
pd  
CC  
CC  
2Y1  
2Y2  
41 2A1  
40 2A2  
39 GND  
38 2A3  
37 2A4  
36 3A1  
35 3A2  
34 GND  
33 3A3  
32 3A4  
Low Power Consumption, 20-µA Max I  
±8-mA Output Drive at 1.8 V  
CC  
GND 10  
2Y3 11  
2Y4 12  
3Y1 13  
3Y2 14  
GND 15  
3Y3 16  
3Y4 17  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description/ordering information  
V
18  
31  
V
CC  
CC  
4Y1 19  
4Y2 20  
GND 21  
4Y3 22  
4Y4 23  
4OE 24  
30 4A1  
29 4A2  
28 GND  
27 4A3  
26 4A4  
25 3OE  
This 16-bit buffer/driver is operational at 0.8-V to  
2.7-V V , but is designed specifically for 1.65-V  
CC  
to 1.95-V V  
operation.  
CC  
The SN74AUC16244 is designed specifically to  
improve the performance and density of 3-state  
memory address drivers, clock drivers, and  
bus-oriented receivers and transmitters.  
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and  
symmetrical active-low output-enable (OE) inputs.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors  
with the bus-hold circuitry is not recommended.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
†
T
PACKAGE  
TSSOP – DGG  
A
MARKING  
AUC16244  
MH244  
Tape and reel  
Tape and reel  
Tape and reel  
SN74AUC16244DGGR  
SN74AUC16244DGVR  
SN74AUC16244GQLR  
–40°C to 85°C TVSOP – DGV  
VFBGA – GQL  
MH244  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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SN74AUC16244GQLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC16245DGVR TI

完全替代

 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC16245DGGR TI

完全替代

 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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