5秒后页面跳转
SN74AUC16245DGVRG4 PDF预览

SN74AUC16245DGVRG4

更新时间: 2024-11-20 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路电视
页数 文件大小 规格书
14页 826K
描述
AUC SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, TVSOP-48

SN74AUC16245DGVRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP, TSSOP48,.25,16针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.7
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:AUCJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:9.7 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.005 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:1.2/2.5 V传播延迟(tpd):3.1 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

SN74AUC16245DGVRG4 数据手册

 浏览型号SN74AUC16245DGVRG4的Datasheet PDF文件第2页浏览型号SN74AUC16245DGVRG4的Datasheet PDF文件第3页浏览型号SN74AUC16245DGVRG4的Datasheet PDF文件第4页浏览型号SN74AUC16245DGVRG4的Datasheet PDF文件第5页浏览型号SN74AUC16245DGVRG4的Datasheet PDF文件第6页浏览型号SN74AUC16245DGVRG4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢃꢊ  
ꢇ ꢈ ꢋꢌꢍ ꢎ ꢌꢅꢀ ꢎ ꢏꢄꢁ ꢀꢆ ꢐ ꢍꢑ ꢐ ꢏ  
ꢒ ꢍꢎ ꢓ ꢔ ꢋꢀꢎꢄꢎ ꢐ ꢕ ꢅꢎ ꢖ ꢅꢎꢀ  
SCES392E − MARCH 2002 − REVISED DECEMBER 2002  
DGG OR DGV PACKAGE  
(TOP VIEW)  
D
D
Member of the Texas Instruments  
WidebusFamily  
Optimized for 1.8-V Operation and is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
3
D
I
Supports Partial-Power-Down Mode  
off  
4
Operation  
5
D
D
D
D
D
Sub 1-V Operable  
6
7
Max t of 2 ns at 1.8 V  
pd  
Low Power Consumption, 20-µA Max I  
V
V
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
CC  
9
8-mA Output Drive at 1.8 V  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
This 16-bit (dual-octal) noninverting bus  
transceiver is operational at 0.8-V to 2.7-V V  
but is designed specifically for 1.65-V to 1.95-V  
,
CC  
V
operation.  
CC  
The  
SN74AUC16245  
is  
designed  
for  
2DIR  
asynchronous communication between data  
buses. The control-function implementation  
minimizes external timing requirements.  
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the  
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)  
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
PACKAGE  
T
A
MARKING  
AUC16245  
MH245  
TSSOP − DGG  
TVSOP − DGV  
VFBGA − GQL  
Tape and reel  
Tape and reel  
Tape and reel  
SN74AUC16245DGGR  
SN74AUC16245DGVR  
SN74AUC16245GQLR  
−40°C to 85°C  
MH245  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢖꢏ ꢕ ꢗꢅ ꢆ ꢎꢍ ꢕ ꢁ ꢗ ꢄꢎꢄ ꢘꢙ ꢚ ꢛꢜ ꢝ ꢞꢟ ꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟ ꢘꢛꢙ ꢧꢞ ꢟꢣ ꢨ  
ꢖꢜ ꢛ ꢧꢢꢡ ꢟ ꢠ ꢡ ꢛꢙ ꢚꢛ ꢜ ꢝ ꢟ ꢛ ꢠ ꢤꢣ ꢡ ꢘꢚ ꢘꢡꢞ ꢟꢘ ꢛꢙꢠ ꢤꢣ ꢜ ꢟꢩ ꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢎꢣꢪ ꢞꢠ ꢍꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ  
ꢠ ꢟ ꢞ ꢙꢧ ꢞ ꢜꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢖꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
Copyright 2002, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

与SN74AUC16245DGVRG4相关器件

型号 品牌 获取价格 描述 数据表
SN74AUC16245GQLR TI

获取价格

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC16373 TI

获取价格

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74AUC16373DGGR TI

获取价格

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74AUC16373DGVR TI

获取价格

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74AUC16373GQLR TI

获取价格

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74AUC16374 TI

获取价格

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374_14 TI

获取价格

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374DGGR TI

获取价格

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374DGVR TI

获取价格

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16374GQLR TI

获取价格

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS