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ꢀꢊ ꢁꢈ ꢋ ꢌ ꢍ ꢎꢊꢁ ꢏꢅꢐ ꢏꢑ ꢀꢊ ꢐ ꢊꢒꢌ ꢎꢁꢄ ꢁꢓ ꢈ ꢄꢐꢌ
SCES368K − SEPTEMBER 2001 − REVISED NOVEMBER 2003
DBV OR DCK PACKAGE
(TOP VIEW)
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1
2
3
5
4
A
B
GND
V
Y
CC
D
I
Supports Partial-Power-Down Mode
off
Operation
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
D
D
D
D
D
Sub 1-V Operable
Max t of 2.2 ns at 1.8 V
pd
Low Power Consumption, 10-µA Max I
3 4
2
GND
B
Y
V
CC
8-mA Output Drive at 1.8 V
1 5
A
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V , but is designed specifically for
CC
1.65-V to 1.95-V V
operation.
CC
The SN74AUC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74AUC1G00YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
SN74AUC1G00YZAR
SN74AUC1G00YEPR
SN74AUC1G00YZPR
Tape and reel
_ _ _UA_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
Tape and reel
Tape and reel
SN74AUC1G00DBVR
SN74AUC1G00DCKR
U00_
UA_
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site.Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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