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SN54AC534W

更新时间： 2024-11-08 22:59:11
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
6页 123K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54AC534W 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：DFP, FL20,.3
针数：20Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.92系列：AC
JESD-30 代码：R-GDFP-F20长度：13.09 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：60000000 Hz最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL20,.3封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 V传播延迟（tpd）：12.5 ns
认证状态：Not Qualified座面最大高度：2.54 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：6.92 mmBase Number Matches：1

SN54AC534W 数据手册

 浏览型号SN54AC534W的Datasheet PDF文件第2页浏览型号SN54AC534W的Datasheet PDF文件第3页浏览型号SN54AC534W的Datasheet PDF文件第4页浏览型号SN54AC534W的Datasheet PDF文件第5页浏览型号SN54AC534W的Datasheet PDF文件第6页 
SN54AC534, SN74AC534  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCAS554A – NOVEMBER 1995 – REVISED MAY 1996  
SN54AC534 . . . J OR W PACKAGE  
SN74AC534 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
3-State Inverting Outputs Drive Bus Lines  
Directly  
Full Parallel Access for Loading  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPs  
description  
GND  
These octal edge-triggered D-type flip-flops  
feature 3-state outputs designed specifically for  
driving highly capacitive or relatively low-imped-  
ance loads. The devices are particularly suitable  
for implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
SN54AC534 . . . FK PACKAGE  
(TOP VIEW)  
3
2 1 20 19  
18  
8D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
On the positive transition of the clock (CLK) input,  
the Q outputs are set to the complements of the  
logic levels set up at the data (D) inputs.  
17 7D  
16  
7Q  
15  
6Q  
14  
6D  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state(highorlowlogiclevels)orahigh-impedance  
state. In the high-impedance state, the outputs  
9 10 11 12 13  
neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the  
capability to drive bus lines without need for interface or pullup components.  
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54AC534 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74AC534 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
↑
↑
L
L
H
L
H or L  
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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