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SN54AC573_06

更新时间： 2024-11-25 04:51:27
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
13页 383K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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SN54AC573_06 数据手册

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SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003  
SN54AC573 . . . J OR W PACKAGE  
SN74AC573 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 9 ns at 5 V  
pd  
3-State Outputs Drive Bus Lines Directly  
1
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4
5
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7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D Inputs.  
SN54AC573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal  
logic state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in a bus-organized system without need for  
interface or pullup components.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14 6Q  
9 10 11 12 13  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC573N  
SN74AC573N  
Tube  
SN74AC573DW  
SN74AC573DWR  
SN74AC573NSR  
SN74AC573DBR  
SN74AC573PW  
SN74AC573PWR  
SNJ54AC573J  
SOIC − DW  
AC573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC573  
AC573  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC573  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC573J  
SNJ54AC573W  
SNJ54AC573FK  
Tube  
SNJ54AC573W  
SNJ54AC573FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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