ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢇ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢇ
ꢊ ꢋꢄꢌꢍ ꢋꢎꢏ ꢐ ꢑ ꢒꢓꢁ ꢎꢋꢆ ꢎꢔ ꢀꢓ ꢆ ꢓꢕꢐ ꢒꢁꢄꢁꢌ ꢖ ꢄꢆꢐ ꢀ
SCAS523D − AUGUST 1995 − REVISED OCTOBER 2003
D
D
4.5-V to 5.5-V V
Operation
D
D
Max t of 8 ns at 5 V
pd
Inputs Are TTL-Voltage Compatible
CC
Inputs Accept Voltages to 5.5 V
SN54ACT00 . . . FK PACKAGE
(TOP VIEW)
SN54ACT00 . . . J OR W PACKAGE
SN74ACT00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
1Y
2A
2B
V
CC
3
2
1
20 19
18
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
4A
NC
4Y
4
5
6
7
8
17
16
NC
2B
15 NC
14 3B
2Y
GND
9 10 11 12 13
8
NC − No internal connection
description/ordering information
The ‘ACT00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A S B or Y = A + B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74ACT00N
SN74ACT00N
Tube
SN74ACT00D
ACT00
Tape and reel
Tape and reel
Tape and reel
Tube
SN74ACT00DR
SN74ACT00NSR
SN74ACT00DBR
SN74ACT00PW
SN74ACT00PWR
SNJ54ACT00J
SNJ54ACT00W
SNJ54ACT00FK
SOP − NS
ACT00
AD00
−40°C to 85°C
SSOP − DB
TSSOP − PW
AD00
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54ACT00J
SNJ54ACT00W
SNJ54ACT00FK
−55°C to 125°C
Tube
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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