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SN54ACT11030FKR PDF预览

SN54ACT11030FKR

更新时间: 2024-11-18 19:59:59
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
5页 63K
描述
ACT SERIES, 8-INPUT NAND GATE, CQCC20, CERAMIC, LCC-20

SN54ACT11030FKR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:ACT
JESD-30 代码:S-CQCC-N20长度:8.89 mm
逻辑集成电路类型:NAND GATE功能数量:1
输入次数:8端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):9.3 ns认证状态:Not Qualified
座面最大高度:2.03 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:8.89 mmBase Number Matches:1

SN54ACT11030FKR 数据手册

 浏览型号SN54ACT11030FKR的Datasheet PDF文件第2页浏览型号SN54ACT11030FKR的Datasheet PDF文件第3页浏览型号SN54ACT11030FKR的Datasheet PDF文件第4页浏览型号SN54ACT11030FKR的Datasheet PDF文件第5页 
54ACT11030, 74ACT11030  
8-INPUT POSITIVE-NAND GATES  
SCLS050 – MARCH 1987 – REVISED APRIL 1993  
54ACT11030 . . . J PACKAGE  
74ACT11030 . . . D OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
C
B
A
D
E
F
V
NC  
G
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
GND  
Y
NC  
NC  
CC  
500-mA Typical Latch-Up Immunity  
at 125°C  
H
8
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
54ACT11030 . . . FK PACKAGE  
(TOP VIEW)  
description  
Thesedevicescontainasingle8-inputNANDgate  
and perform the following Boolean functions in  
positive logic:  
3
2
1
20 19  
18  
G
D
NC  
C
4
5
6
7
8
17  
16  
15  
14  
NC  
H
Y = A B C D E F G H or  
Y = A + B + C + D + E + F + G + H  
NC  
NC  
NC  
B
9 10 11 12 13  
The 54ACT11030 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The 74ACT11030 is characterized for  
operation from 40°C to 85°C.  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
A THRU H  
OUTPUT  
Y
All inputs H  
L
One or more inputs L  
H
logic symbol  
logic diagram (positive logic)  
3
A
3
A
&
2
2
B
B
1
1
C
C
14  
D
14  
D
5
5
Y
13  
E
13  
E
Y
12  
F
12  
F
9
9
G
G
8
8
H
H
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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