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SN54ACT10J PDF预览

SN54ACT10J

更新时间: 2024-11-17 22:59:11
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路输入元件
页数 文件大小 规格书
5页 82K
描述
TRIPLE 3-INPUT POSITIVE-NAND GATES

SN54ACT10J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:CERAMIC, DIP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.3Is Samacsys:N
系列:ACTJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE功能数量:3
输入次数:3端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN54ACT10J 数据手册

 浏览型号SN54ACT10J的Datasheet PDF文件第2页浏览型号SN54ACT10J的Datasheet PDF文件第3页浏览型号SN54ACT10J的Datasheet PDF文件第4页浏览型号SN54ACT10J的Datasheet PDF文件第5页 
SN54ACT10, SN74ACT10  
TRIPLE 3-INPUT POSITIVE-NAND GATES  
SCAS526A – AUGUST 1995 – REVISED APRIL 1996  
SN54ACT10 . . . J OR W PACKAGE  
SN74ACT10 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
1A  
1B  
2A  
2B  
2C  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPS  
1C  
1Y  
3A  
3B  
3C  
3Y  
2Y  
GND  
8
description  
The ’ACT10 contain three independent 3-input  
NAND gates. The devices perform the Boolean  
functions Y = A B C or Y = A + B + C in positive  
logic.  
SN54ACT10 . . . FK PACKAGE  
(TOP VIEW)  
The SN54ACT10 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ACT10 is characterized for  
operation from 40°C to 85°C.  
3
2
1
20 19  
18  
1Y  
NC  
3A  
NC  
3B  
2A  
NC  
2B  
4
5
6
7
8
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
NC  
2C  
INPUTS  
9 10 11 12 13  
OUTPUT  
Y
A
H
L
B
H
X
L
C
H
X
X
L
L
H
H
H
NC – No internal connection  
X
X
X
logic symbol  
logic diagram, each gate (positive logic)  
1
1
1A  
1A  
&
12  
2
12  
6
1Y  
1B  
1C  
2
1Y  
2Y  
3Y  
13  
1B  
13  
1C  
3
4
5
2A  
2B  
2C  
3
6
2A  
4
2Y  
3Y  
2B  
5
11  
10  
9
2C  
3A  
3B  
3C  
8
8
11  
3A  
10  
3B  
9
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, DB, J, N, PW, and W packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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