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SN54AC573W PDF预览

SN54AC573W

更新时间: 2024-11-26 22:59:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路输出元件
页数 文件大小 规格书
6页 124K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54AC573W 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:CERAMIC, FP-20针数:20
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:N其他特性:BROADSIDE VERSION OF 373
系列:ACJESD-30 代码:R-GDFP-F20
长度:13.09 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL20,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:3.3/5 V
Prop。Delay @ Nom-Sup:16.5 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified座面最大高度:2.54 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
宽度:6.92 mmBase Number Matches:1

SN54AC573W 数据手册

 浏览型号SN54AC573W的Datasheet PDF文件第2页浏览型号SN54AC573W的Datasheet PDF文件第3页浏览型号SN54AC573W的Datasheet PDF文件第4页浏览型号SN54AC573W的Datasheet PDF文件第5页浏览型号SN54AC573W的Datasheet PDF文件第6页 
SN54AC573, SN74AC573  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996  
SN54AC573 . . . J OR W PACKAGE  
SN74AC573 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
3-State Outputs Drive Bus Lines Directly  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
Small-Outline (DW) Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPs  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
description  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND 10  
11 LE  
SN54AC573 . . . FK PACKAGE  
(TOP VIEW)  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D Inputs.  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
17  
16  
15  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the high-imped-  
ance state. In the high-impedance state, the  
outputs neither load nor drive the bus lines  
significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in a bus-organized system without need for  
interface or pullup components.  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54AC573 is characterized for operation over the full military temperature range of –55 C to 125 C.  
The SN74AC573 is characterized for operation from –40 C to 85 C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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