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SN54AC74W PDF预览

SN54AC74W

更新时间: 2024-11-24 22:59:11
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
7页 113K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN54AC74W 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DFP包装说明:DFP, FL14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.1
系列:ACJESD-30 代码:R-CDFP-F14
长度:9.21 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:100000000 Hz
最大I(ol):0.012 A位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装等效代码:FL14,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
传播延迟(tpd):17.5 ns认证状态:Not Qualified
座面最大高度:2.03 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.29 mm
最小 fmax:95 MHzBase Number Matches:1

SN54AC74W 数据手册

 浏览型号SN54AC74W的Datasheet PDF文件第2页浏览型号SN54AC74W的Datasheet PDF文件第3页浏览型号SN54AC74W的Datasheet PDF文件第4页浏览型号SN54AC74W的Datasheet PDF文件第5页浏览型号SN54AC74W的Datasheet PDF文件第6页浏览型号SN54AC74W的Datasheet PDF文件第7页 
SN54AC74, SN74AC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996  
SN54AC74 . . . J OR W PACKAGE  
SN74AC74 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), Flat  
(W), and DIP (J,N) Packages  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1CLK  
1PRE  
1Q  
2CLK  
2PRE  
2Q  
description  
1Q  
GND  
2Q  
8
The ’AC74 are dual positive-edge-triggered  
D-type flip-flops.  
Alowlevelatthepreset(PRE)orclear(CLR)input  
sets or resets the outputs, regardless of the levels  
of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) input meeting  
the setup-time requirements is transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of the  
clock pulse. Following the hold-time interval, data  
at D can be changed without affecting the levels  
at the outputs.  
SN54AC74 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
15  
14  
2CLK  
NC  
1PRE  
NC  
2PRE  
1Q  
9 10 11 12 13  
The SN54AC74 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74AC74 is characterized for  
operation from –40°C to 85°C.  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
CLR  
PRE  
L
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
This configuration is unstable; that is, it does not  
persist when either PRE or CLR returns to its  
inactive (high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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