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SN54AC564_06

更新时间： 2024-11-25 04:51:27
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
13页 383K
描述
OCTAL D-TYPE EDGE-TRIGGERDE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54AC564_06 数据手册

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SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003  
SN54AC564 . . . J OR W PACKAGE  
SN74AC564 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 9 ns at 5 V  
pd  
3-State Inverting Outputs Drive Bus Lines  
Directly  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
19 1Q  
1
2
3
4
5
6
7
8
9
10  
20  
18  
17  
16  
15  
14  
13  
12  
11  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
D
Full Parallel Access for Loading  
D
Flow-Through Architecture to Optimize  
PCB Layout  
description/ordering information  
The ’AC564 devices are octal D-type  
edge-triggered flip-flops that feature inverting  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
GND  
SN54AC564 . . . FK PACKAGE  
(TOP VIEW)  
On the positive transition of the clock (CLK) input,  
the Q outputs are set to the inverse logic levels set  
up at the data (D) inputs.  
3
2
1
20 19  
18  
3D  
4D  
5D  
6D  
7D  
2Q  
17 3Q  
4
5
6
7
8
16  
15  
14  
4Q  
5Q  
6Q  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
9 10 11 12 13  
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC564N  
SN74AC564N  
Tube  
SN74AC564DW  
SN74AC564DWR  
SN74AC564NSR  
SN74AC564DBR  
SN74AC564PW  
SN74AC564PWR  
SNJ54AC564J  
SOIC − DW  
AC564  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC564  
AC564  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC564  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC564J  
SNJ54AC564W  
SNJ54AC564FK  
Tube  
SNJ54AC564W  
SNJ54AC564FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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