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SN54AC563J PDF预览

SN54AC563J

更新时间： 2024-11-06 20:10:59
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
6页 119K
描述
AC SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20

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SN54AC563J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknown风险等级：5.84
其他特性：BROADSIDE VERSION OF 533系列：AC
JESD-30 代码：R-GDIP-T20长度：24.195 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：11.5 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN54AC563J 数据手册

 浏览型号SN54AC563J的Datasheet PDF文件第2页浏览型号SN54AC563J的Datasheet PDF文件第3页浏览型号SN54AC563J的Datasheet PDF文件第4页浏览型号SN54AC563J的Datasheet PDF文件第5页浏览型号SN54AC563J的Datasheet PDF文件第6页 
SN54AC563, SN74AC563  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS552A – NOVEMBER 1995 – REVISED MAY 1996  
SN54AC563 . . . J OR W PACKAGE  
SN74AC563 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
3-State Inverting Outputs Drive Bus Lines  
Directly  
Full Parallel Access for Loading  
Flow-Through Architecture to Optimize  
PCB Layout  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPs  
13 7Q  
12 8Q  
11  
GND  
LE  
description  
SN54AC563 . . . FK PACKAGE  
(TOP VIEW)  
The ’AC563 are octal D-type transparent latches  
with 3-state outputs. When the latch-enable (LE)  
input is high, the  
Q outputs follow the  
complements of the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the inverse  
logic levels set up at the D inputs.  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
17  
16  
15  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the high-imped-  
ance state. In the high-impedance state, the  
outputs neither load nor drive the bus lines  
significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
9 10 11 12 13  
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN54AC563 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74AC563 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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