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SI53019-A01AGMR PDF预览

SI53019-A01AGMR

更新时间: 2024-11-06 15:51:11
品牌 Logo 应用领域
芯科 - SILICON 驱动逻辑集成电路
页数 文件大小 规格书
36页 983K
描述
PLL Based Clock Driver, 53019 Series, 38 True Output(s), 0 Inverted Output(s), QFN-72

SI53019-A01AGMR 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:1.66
Is Samacsys:N系列:53019
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-XQCC-N72
长度:10 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:72实输出次数:38
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度:0.95 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

SI53019-A01AGMR 数据手册

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Si53019-A01A  
19-OUTPUT PCIE GEN 3 BUFFER  
Features  
Nineteen 0.7 V current-mode,  
Spread spectrum tolerable  
HCSL PCIe Gen 3 outputs  
50 ps output-to-output skew  
100 MHz /133 MHz PLL  
operation, supports PCIe and  
QPI  
Fixed 0 ps input to output delay  
Low phase jitter (Intel QPI, PCIe  
Gen 1/Gen 2/Gen 3/Gen 4  
common clock compliant  
PLL bandwidth SW SMBUS  
programming overrides the latch  
value from HW pin  
Gen 3 SRNS Compliant  
100 ps input-to-output delay  
9 selectable SMBus addresses  
Fixed external feedback path  
8 dedicated OE pin  
Extended Temperature:  
–40 to 85 °C  
Ordering Information:  
Package: 72-pin QFN  
See page 32.  
PLL or bypass mode  
Applications  
Pin Assignments  
Server  
Data Center  
Storage  
Network Security  
Description  
The Si53019-A01A is a 19-output, current mode HCSL differential clock  
buffer that meets all of the performance requirements of the Intel  
DB1900Z specification. The device is optimized for distributing reference  
®
clocks for Intel QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/  
Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel  
SMI) applications. The VCO of the device is optimized to support  
100 MHz and 133 MHz operation. Each differential output can be enabled  
2
through I C for maximum flexibility and power savings. Measuring PCIe  
clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.  
Download it for free at www.silabs.com/pcie-learningcenter.  
Patents pending  
Rev. 1.5 7/17  
Copyright © 2017 by Silicon Laboratories  
Si53019-A01A  

SI53019-A01AGMR 替代型号

型号 品牌 替代类型 描述 数据表
SI53019-A01AGM SILICON

完全替代

PLL Based Clock Driver, 53019 Series, 38 True Output(s), 0 Inverted Output(s), QFN-72

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