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SI5310-BM

更新时间: 2024-11-26 03:43:31
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芯科 - SILICON 时钟
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26页 518K
描述
PRECISION CLOCK MULTIPLIER/REGENERATOR IC

SI5310-BM 数据手册

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Si5310  
PRECISION CLOCK MULTIPLIER/REGENERATOR IC  
Features  
Complete precision clock multiplier and clock regenerator device:  
„ Performs clock multiplication to one „ Regenerates a “clean”, jitter-  
of two frequency ranges:  
attenuated version of input clock  
150–167 MHz or 600–668 MHz  
„ DSPLL™ technology provides  
„ Jitter generation as low as  
superior jitter performance  
Ordering Information:  
0.5 psrms for 622 MHz output  
„ Small footprint: 4 x 4 mm  
„ Low power: 310 mW typical  
See page 21.  
„ Accepts input clock from  
9.4–668 MHz  
„ ROHS-compliant Pb-free  
packaging option available  
Pin Assignments  
Si5310  
Applications  
„ SONET/SDH systems  
„ Terabit routers  
„ Optical transceiver modules  
„ Gigabit Ethernet systems  
„ Fibre channel  
„ Digital cross connects  
20 19 18 17 16  
Description  
REXT  
VDD  
1
2
3
4
5
15  
14  
13  
12  
11  
PWRDN  
VDD  
The Si5310 is a fully integrated low-power clock multiplier and clock  
regenerator IC. The clock multiplier generates an output clock that is an  
integer multiple of the input clock. The clock regenerator operates  
simultaneously, creating a “clean” version of the input clock by using the  
clock synthesis phase-locked loop (PLL) to remove unwanted jitter and  
square up the input clock’s rising and falling edges. The Si5310 uses  
GND  
Pad  
GND  
CLKOUT+  
CLKOUT–  
VDD  
REFCLK+  
REFCLK–  
6
7
8
9
10  
®
Silicon Laboratories patented DSPLL architecture to achieve superior  
jitter performance while eliminating the analog loop filter found in  
traditional PLL designs with a digital signal-processing algorithm.  
The Si5310 represents a new standard in low jitter, small size, low power,  
and ease-of-use for clock devices. It operates from a single 2.5 V supply  
over the industrial temperature range (–40 to 85 °C).  
Functional Block Diagram  
2
CLKOUT+  
CLKOUT–  
Regeneration  
BUF  
BUF  
Calibration  
PWRDN/CAL  
DSPLL®  
Phase-Locked  
Loop  
2
CLKIN+  
CLKIN–  
2
MULTOUT+  
MULTOUT–  
BUF  
LOL  
Bias Gen  
2
REXT  
REFCLK+  
REFCLK–  
MULTSEL  
Rev. 1.2 8/06  
Copyright © 2006 by Silicon Laboratories  
Si5310  

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