Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> SI5310-GMR

SI5310-GMR

更新时间： 2024-11-06 12:59:39

品牌	Logo	应用领域
芯科 - SILICON		时钟
页数	文件大小	规格书
26页	518K
描述
Clock Recovery Circuit, 1-Func, 4 X 4 MM, ROHS COMPLIANT, MLP-20

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技术参数
数据手册

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SI5310-GMR 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DFN	包装说明：	VQCCN,
针数：	20	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.82
JESD-30 代码：	S-XQCC-N20	长度：	4 mm
功能数量：	1	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	VQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, VERY THIN PROFILE
认证状态：	Not Qualified	座面最大高度：	0.9 mm
标称供电电压：	2.5 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	4 mm
Base Number Matches：	1

SI5310-GMR 数据手册

Si5310

PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Features

Complete precision clock multiplier and clock regenerator device:

Performs clock multiplication to one Regenerates a “clean”, jitter-

of two frequency ranges:

attenuated version of input clock

150–167 MHz or 600–668 MHz

DSPLL™ technology provides

Jitter generation as low as

superior jitter performance

Ordering Information:

0.5 ps_rmsfor 622 MHz output

Small footprint: 4 x 4 mm

Low power: 310 mW typical

See page 21.

Accepts input clock from

9.4–668 MHz

ROHS-compliant Pb-free

packaging option available

Pin Assignments

Si5310

Applications

SONET/SDH systems

Terabit routers

Optical transceiver modules

Gigabit Ethernet systems

Fibre channel

Digital cross connects

20 19 18 17 16

Description

REXT

VDD

PWRDN

VDD

The Si5310 is a fully integrated low-power clock multiplier and clock

regenerator IC. The clock multiplier generates an output clock that is an

integer multiple of the input clock. The clock regenerator operates

simultaneously, creating a “clean” version of the input clock by using the

clock synthesis phase-locked loop (PLL) to remove unwanted jitter and

square up the input clock’s rising and falling edges. The Si5310 uses

GND

Pad

GND

CLKOUT+

CLKOUT–

VDD

REFCLK+

REFCLK–

Silicon Laboratories patented DSPLL architecture to achieve superior

jitter performance while eliminating the analog loop filter found in

traditional PLL designs with a digital signal-processing algorithm.

The Si5310 represents a new standard in low jitter, small size, low power,

and ease-of-use for clock devices. It operates from a single 2.5 V supply

over the industrial temperature range (–40 to 85 °C).

Functional Block Diagram

CLKOUT+

CLKOUT–

Regeneration

BUF

Calibration

PWRDN/CAL

DSPLL^®

Phase-Locked

Loop

CLKIN+

CLKIN–

MULTOUT+

MULTOUT–

BUF

LOL

Bias Gen

REXT

REFCLK+

REFCLK–

MULTSEL

Rev. 1.2 8/06

Si5310

12 3 4 5 6 7...26

中文翻译

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与SI5310-GMR相关器件

型号	品牌	获取价格	描述	数据表
SI5311	ETC	获取价格	PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC
SI53112-A00AGM	SILICON	获取价格	PLL Based Clock Driver, 53112 Series, 24 True Output(s), 0 Inverted Output(s), LEAD FREE,
SI53112-A00AGMR	SILICON	获取价格	PLL Based Clock Driver, 53112 Series, 24 True Output(s), 0 Inverted Output(s), LEAD FREE,
SI53115-A01AGM	SILICON	获取价格	PLL Based Clock Driver, 53115 Series, 30 True Output(s), 0 Inverted Output(s), LEAD FREE,
SI53115-A01AGMR	SILICON	获取价格	PLL Based Clock Driver, 53115 Series, 30 True Output(s), 0 Inverted Output(s), LEAD FREE,
SI53119-A03A	SILICON	获取价格	PLL or bypass mode
SI53119-A03AGM	SILICON	获取价格	PLL Based Clock Driver, 53119 Series, 38 True Output(s), 0 Inverted Output(s), QFN-72
Si53119-A03AGMR	SILICON	获取价格	PLL or bypass mode
SI5311-BM	ETC	获取价格	PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC
SI5311-H	AUK	获取价格	IRED

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