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SI53112-A00AGM PDF预览

SI53112-A00AGM

更新时间: 2024-11-23 21:14:35
品牌 Logo 应用领域
芯科 - SILICON 驱动逻辑集成电路
页数 文件大小 规格书
35页 1447K
描述
PLL Based Clock Driver, 53112 Series, 24 True Output(s), 0 Inverted Output(s), LEAD FREE, MO-220, QFN-64

SI53112-A00AGM 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:2.25
系列:53112输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N64长度:9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:64
实输出次数:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):4.5 ns
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:0.95 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:9 mm
Base Number Matches:1

SI53112-A00AGM 数据手册

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Si53112  
DB1200ZL 12-OUTPUT PCI  
E
GEN 3 BUFFER  
Features  
Twelve 0.7 V low-power, push- PLL or bypass mode  
pull, HCSL-compatible  
PCIe Gen 3 outputs  
Spread spectrum tolerable  
1.05 to 3.3 V I/O supply voltage  
50 ps output-to-output skew  
50 ps cyc-cyc jitter (PLL mode)  
Individual OE HW pins for each  
output clock  
100 MHz /133 MHz PLL  
operation, supports PCIe and  
QPI  
Low phase jitter (Intel QPI, PCIe  
Gen 1/2/3/4 common clock  
compliant)  
PLL bandwidth SW SMBUS  
programming overrides the latch  
value from HW pin  
Gen 3 SRNS Compliant  
100 ps input-to-output delay  
Ordering Information:  
Extended Temperature:  
See page 30.  
9 selectable SMBUS addresses  
–40 to 85 °C  
SMBus address configurable to  
allow multiple buffers in a single  
control network 3.3 V supply  
voltage operation  
Package: 64-pin QFN  
Patents pending  
For higher output devices or  
variations of this device, contact  
Silicon Labs  
Applications  
Server  
Datacenter  
Storage  
Enterprise Switches and Routers  
Description  
The Si53112 is a low-power, 12-output, differential clock buffer that meets  
all of the performance requirements of the Intel DB1200ZL specification.  
®
The device is optimized for distributing reference clocks for Intel  
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,  
SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)  
applications. The VCO of the device is optimized to support 100 MHz and  
133 MHz operation. Each differential output has a dedicated hardware  
output enable pin for maximum flexibility and power savings. Measuring  
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter  
Tool. Download it for free at www.silabs.com/pcie-learningcenter.  
Rev. 1.1 12/15  
Copyright © 2015 by Silicon Laboratories  
Si53112  

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