Datasheet > PHN1018/T3

PHN1018/T3

更新时间： 2024-09-27 23:27:35

品牌	Logo	应用领域
其他 - ETC		晶体晶体管
页数	文件大小	规格书
7页	92K
描述
TRANSISTOR MOSFET SOT-96

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中文翻译

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数据手册

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PHN1018/T3 数据手册

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Low on-state resistance

• Fast switching

• Low-profile surface mount

package

V_DSS= 25 V

I_D= 9.6 A

_DS(ON)≤ 18 mΩ (V_GS= 10 V)

• Logic level compatible

R_DS(ON)≤ 21 mΩ (V_GS= 5 V)

GENERAL DESCRIPTION

PINNING

SOT96-1 (SO8)

N-channel enhancement mode

logic level field-effect power

transistor in a surface mounting

plastic package using ’trench’

technology.

DESCRIPTION

1-3

source

gate

Application:-

5-8

drain

•

High frequency computer

pin 1 index

motherboard d.c. to d.c. converters

The PHN1018 is supplied in the

SOT96-1 (SO8) surface mounting

package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

Drain-source voltage

Drain-gate voltage

T_j= 25 ˚C to 150˚C

T_j= 25 ˚C to 150˚C;

R_GS= 20 kΩ

V_GS

V_GSM

Gate-source voltage (DC)

Gate-source voltage (pulse peak

value)

± 15

± 20

I_D

Drain current (t_p≤ 10 s)

T_a= 25 ˚C

T_a= 70 ˚C

T_a= 25 ˚C

T_a= 70 ˚C

9.6

7.7

2.5

1.6

150

˚C

I_DM

P_tot

Drain current (pulse peak value)

Total power dissipation

T_j, T_stg

Operating junction and storage

temperature

- 55

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-a}

Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec

to ambient

K/W

R_{th j-a}

Thermal resistance junction Surface mounted, FR4 board

to ambient

150

K/W

October 1999

Rev 1.200

12 3 4 5 6 7

中文翻译

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