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NTMSD2P102LR2/D

更新时间： 2024-01-05 23:22:20
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
12页 129K
描述
FETKY?

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NTMSD2P102LR2/D 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOT
包装说明：LEAD FREE, CASE 751-07, SOIC-8针数：8
Reach Compliance Code：unknown风险等级：5.33
其他特性：LOGIC LEVEL COMPATIBLE配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：20 V最大漏极电流 (ID)：2.3 A
最大漏源导通电阻：0.09 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：175 pFJESD-30 代码：R-PDSO-G8
JESD-609代码：e3湿度敏感等级：NOT SPECIFIED
元件数量：1端子数量：8
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260极性/信道类型：P-CHANNEL
认证状态：COMMERCIAL表面贴装：YES
端子面层：MATTE TIN端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：40
晶体管应用：SWITCHING晶体管元件材料：SILICON

NTMSD2P102LR2/D 数据手册

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NTMSD2P102LR2  
Product Preview  
FETKY  
Power MOSFET and Schottky Diode  
Dual SO–8 Package  
Features  
http://onsemi.com  
• High Efficiency Components in a Single SO–8 Package  
• High Density Power MOSFET with Low R  
,
DS(on)  
Schottky Diode with Low V  
F
MOSFET  
–2.3 AMPERES  
–20 VOLTS  
• Logic Level Gate Drive  
• Independent Pin–Outs for MOSFET and Schottky Die  
Allowing for Flexibility in Application Use  
• Less Component Placement for Board Space Savings  
90 mW @ VGS = –4.5 V  
• SO–8 Surface Mount Package,  
Mounting Information for SO–8 Package Provided  
Applications  
SCHOTTKY DIODE  
2.0 AMPERES  
20 VOLTS  
• Power Management in Portable and Battery–Powered Products, i.e.:  
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones  
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
Unit  
58 mV @ IF = 2.0 A  
Drain–to–Source Voltage  
V
–20  
V
V
DSS  
Gate–to–Source Voltage – Continuous  
V
"10  
GS  
Thermal Resistance –  
Junction–to–Ambient (Note 1.)  
R
P
I
I
175  
0.71  
–2.3  
–1.45  
–9.0  
°C/W  
W
A
A
A
θ
JA  
1
2
8
7
A
A
S
G
C
C
D
D
Total Power Dissipation @ T = 25°C  
A
D
8
Continuous Drain Current @ T = 25°C  
A
D
Continuous Drain Current @ T = 100°C  
6
A
D
1
Pulsed Drain Current (Note 4.)  
I
DM  
3
Thermal Resistance –  
Junction–to–Ambient (Note 2.)  
SO–8  
CASE 751  
STYLE 18  
4
5
R
P
I
I
105  
1.19  
–2.97  
–1.88  
–12  
°C/W  
W
A
A
A
θ
JA  
Total Power Dissipation @ T = 25°C  
TOP VIEW  
A
D
Continuous Drain Current @ T = 25°C  
A
D
Continuous Drain Current @ T = 100°C  
A
D
Pulsed Drain Current (Note 4.)  
I
DM  
MARKING DIAGRAM  
& PIN ASSIGNMENTS  
Thermal Resistance –  
Junction–to–Ambient (Note 3.)  
R
P
I
I
62.5  
2.0  
–3.85  
–2.43  
–15  
°C/W  
W
A
A
A
θ
JA  
Total Power Dissipation @ T = 25°C  
1
2
8
7
A
D
Anode  
Anode  
Source  
Gate  
Cathode  
Cathode  
Drain  
Continuous Drain Current @ T = 25°C  
A
D
Continuous Drain Current @ T = 100°C  
A
D
E2P102L  
LYWW  
3
4
6
5
Pulsed Drain Current (Note 4.)  
I
DM  
Operating and Storage  
Temperature Range  
T , T  
J
–55 to  
+150  
°C  
stg  
Drain  
(Top View)  
Single Pulse Drain–to–Source Avalanche  
E
350  
mJ  
AS  
Energy – Starting T = 25°C (V  
=
J
DD  
E2P102L= Device Code  
–20 Vdc, V = –4.5 Vdc, Peak I =  
GS  
L
L
= Assembly Location  
–5.0 Apk, L = 28 mH, R = 25 Ω)  
G
Y
= Year  
Maximum Lead Temperature for Soldering  
Purposes, 1/8″ from case for 10 seconds  
T
L
260  
°C  
WW  
= Work Week  
1. Minimum FR–4 or G–10 PCB, Steady State.  
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single  
sided), Steady State.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
3. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single  
sided), t ≤ 10 seconds.  
NTMSD2P102LR2  
SO–8  
2500/Tape & Reel  
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
November, 2000 – Rev. 0  
NTMSD2P102LR2/D  
1234567...12

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