NTD20N06L, NTDV20N06L
Power MOSFET
20 A, 60 V, Logic Level, N−Channel
DPAK/IPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
www.onsemi.com
V
R
TYP
I MAX
D
(BR)DSS
DS(on)
Features
20 A
(Note 1)
60 V
39 mW@5.0 V
• AEC Q101 Qualified − NTDV20N06L
• These Devices are Pb−Free and are RoHS Compliant
D
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
N−Channel
G
S
4
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol Value
Unit
Vdc
Vdc
Vdc
4
Drain−to−Source Voltage
V
V
60
60
DSS
Drain−to−Gate Voltage (R = 10 MW)
1
GS
DGR
2
1
2
3
3
Gate−to−Source Voltage
− Continuous
V
V
15
20
GS
GS
DPAK
IPAK
− Non−repetitive (t v10 ms)
p
CASE 369C
STYLE 2
CASE 369D
STYLE 2
Drain Current
− Continuous @ T = 25°C
I
I
20
10
60
Adc
Apk
A
D
D
− Continuous @ T = 100°C
A
MARKING DIAGRAMS
& PIN ASSIGNMENTS
− Single Pulse (t v10 ms)
p
I
DM
Total Power Dissipation @ T = 25°C
P
D
60
W
W/°C
W
4
4
A
Derate above 25°C
0.40
1.88
1.36
Drain
Drain
Total Power Dissipation @ T = 25°C (Note 1)
A
Total Power Dissipation @ T = 25°C (Note 2)
A
W
Operating and Storage Temperature Range
T , T
−55 to
+175
°C
J
stg
Single Pulse Drain−to−Source Avalanche
E
AS
128
mJ
2
Energy − Starting T = 25°C
1
Gate
J
3
Drain
(V = 25 Vdc, V = 5.0 Vdc,
DD
GS
Source
1
2
3
L = 1.0 mH, I (pk) = 16 A, V = 60 Vdc)
L
DS
Gate Drain Source
Thermal Resistance
°C/W
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
R
R
R
2.5
80
110
A
Y
WW
20N6L
G
= Assembly Location*
q
JC
JA
JA
= Year
q
= Work Week
= Device Code
= Pb−Free Package
q
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
260
°C
L
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2
1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in ).
2. When surface mounted to an FR4 board using recommended pad size,
2
(Cu Area 0.412 in ).
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2017 − Rev. 5
NTD20N06L/D