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NSBC113EDXV6T1G PDF预览

NSBC113EDXV6T1G

更新时间： 2024-11-26 11:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 开关光电二极管小信号双极晶体管
页数 文件大小 规格书
21页 140K
描述
50V Dual NPN Bipolar Digital Transistor

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中文翻译

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NSBC113EDXV6T1G 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：SMALL OUTLINE, R-PDSO-F6针数：6
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：5.73其他特性：BUILT IN BIAS RESISTOR RATIO IS 1
最大集电极电流 (IC)：0.1 A集电极-发射极最大电压：50 V
配置：SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR最小直流电流增益 (hFE)：3
JESD-30 代码：R-PDSO-F6JESD-609代码：e3
湿度敏感等级：1元件数量：2
端子数量：6封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：NPN
最大功率耗散 (Abs)：0.5 W认证状态：Not Qualified
子类别：BIP General Purpose Small Signal表面贴装：YES
端子面层：Tin (Sn)端子形式：FLAT
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

NSBC113EDXV6T1G 数据手册

 浏览型号NSBC113EDXV6T1G的Datasheet PDF文件第2页浏览型号NSBC113EDXV6T1G的Datasheet PDF文件第3页浏览型号NSBC113EDXV6T1G的Datasheet PDF文件第4页浏览型号NSBC113EDXV6T1G的Datasheet PDF文件第5页浏览型号NSBC113EDXV6T1G的Datasheet PDF文件第6页浏览型号NSBC113EDXV6T1G的Datasheet PDF文件第7页 
MUN5211DW1T1 Series  
Preferred Devices  
Dual Bias Resistor  
Transistors  
NPN Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
The BRT (Bias Resistor Transistor) contains a single transistor with  
a monolithic bias network consisting of two resistors; a series base  
resistor and a base−emitter resistor. These digital transistors are  
designed to replace a single device and its external resistor bias  
network. The BRT eliminates these individual components by  
integrating them into a single device. In the MUN5211DW1T1 series,  
two BRT devices are housed in the SOT−363 package which is ideal  
for low power surface mount applications where board space is at a  
premium.  
http://onsemi.com  
(3)  
(2)  
(1)  
R
1
R
2
Q
1
Q
2
R
2
R
1
Features  
(4)  
(5)  
(6)  
• Simplifies Circuit Design  
• Reduces Board Space  
• Reduces Component Count  
• Pb−Free Packages are Available  
1
MAXIMUM RATINGS  
(T = 25°C unless otherwise noted, common for Q and Q )  
A
SOT−363  
CASE 419B  
STYLE 1  
1
2
Rating  
Symbol  
Value  
50  
Unit  
Vdc  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
V
V
CBO  
CEO  
50  
Vdc  
MARKING DIAGRAM  
I
100  
mAdc  
C
6
THERMAL CHARACTERISTICS  
xx M G  
Characteristic  
(One Junction Heated)  
G
Symbol  
Max  
Unit  
Total Device Dissipation  
P
187 (Note 1)  
256 (Note 2)  
1.5 (Note 1)  
2.0 (Note 2)  
mW  
1
D
T = 25°C  
A
Derate above 25°C  
mW/°C  
°C/W  
xx  
M
G
= Device Code  
= Date Code*  
= Pb−Free Package  
Thermal Resistance,  
Junction-to-Ambient  
R
q
670 (Note 1)  
490 (Note 2)  
JA  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may  
vary depending upon manufacturing location.  
Characteristic  
(Both Junctions Heated)  
Symbol  
Max  
Unit  
Total Device Dissipation  
P
250 (Note 1)  
385 (Note 2)  
2.0 (Note 1)  
3.0 (Note 2)  
mW  
D
T = 25°C  
A
DEVICE MARKING INFORMATION  
See specific marking information in the device marking table  
on page 2 of this data sheet.  
Derate above 25°C  
mW/°C  
°C/W  
°C/W  
°C  
Thermal Resistance,  
Junction-to-Ambient  
R
q
493 (Note 1)  
325 (Note 2)  
JA  
Preferred devices are recommended choices for future use  
and best overall value.  
Thermal Resistance,  
Junction-to-Lead  
R
q
188 (Note 1)  
208 (Note 2)  
JL  
Junction and Storage Temperature  
T , T  
J
−55 to +150  
stg  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. FR−4 @ Minimum Pad  
2. FR−4 @ 1.0 x 1.0 inch Pad  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
December, 2005 − Rev. 7  
MUN5211DW1T1/D  
 
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中文翻译

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