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NE6510179A PDF预览

NE6510179A

更新时间: 2024-11-13 22:29:07
品牌 Logo 应用领域
CEL 晶体射频场效应晶体管放大器
页数 文件大小 规格书
10页 287K
描述
NECs 3W, L&S-BAND MEDIUM POWER GaAs HJ-FET

NE6510179A 技术参数

生命周期:Obsolete包装说明:MICROWAVE, R-PQMW-F4
针数:4Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.62
Is Samacsys:N外壳连接:SOURCE
配置:SINGLE最小漏源击穿电压:5.5 V
最大漏极电流 (ID):2.8 AFET 技术:HETERO-JUNCTION
最高频带:S BANDJESD-30 代码:R-PQMW-F4
元件数量:1端子数量:4
工作模式:DEPLETION MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:MICROWAVE
极性/信道类型:N-CHANNEL认证状态:Not Qualified
表面贴装:YES端子形式:FLAT
端子位置:QUAD晶体管应用:AMPLIFIER
晶体管元件材料:GALLIUM ARSENIDEBase Number Matches:1

NE6510179A 数据手册

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NEC's 3W, L&S-BAND  
MEDIUM POWER GaAs HJ-FET  
NE6510179A  
FEATURES  
OUTLINE DIMENSIONS (Units in mm)  
• LOW COST PLASTIC SURFACE MOUNT PACKAGE  
Available on Tape and Reel  
PACKAGE OUTLINE 79A  
1.5 – 0.2  
4.2 MAX  
• USABLE TO 3.7 GHz:  
Source  
Fixed Wireless Access, ISM, WLL, MMDS, IMT-2000,  
PCS  
Source  
Drain  
Drain  
Gate  
Gate  
• HIGH OUTPUT POWER:  
35 dBm TYP with 5.0 V Vdc  
32.5 dBm TYP with 3.5 V Vdc  
• HIGH LINEAR GAIN:  
10 dB TYP at 1.9 GHz  
0.4 – 0.15  
5.7 MAX  
0.8 MAX  
3.6 – 0.2  
• LOW THERMAL RESISTANCE:  
5°C/W  
BOTTOM VIEW  
DESCRIPTION  
Note: Unless otherwise specified, tolerance is ±0.2 mm  
NEC's NE6510179A is a GaAs HJ-FET designed for medium  
power mobile communications, Fixed Wireless Access, ISM,  
WLL, PCS, IMT-2000, and MMDS transmitter and subscriber  
applications. It is capable of delivering 1.8 watts of output  
power(C/W) at 3.5 V and 3 Watts of ouptut power (CW) at 5 V  
with high linear gain, high efficiency, and excellent linearity.  
Reliability and performance uniformity are assured by NEC's  
stringent quality and control procedures.  
ELECTRICAL CHARACTERISTICS (TC = 25°C)  
PART NUMBER  
NE6510179A  
79A  
PACKAGE OUTLINE  
SYMBOLS  
POUT  
GL  
CHARACTERISTICS  
UNITS  
dBm  
dB  
MIN  
TYP  
32.5  
10.0  
58  
MAX  
TEST CONDITIONS  
Output Power  
Linear Gain1  
31.5  
f = 1900 MHz, VDS = 3.5 V,  
Pin = +25 dBm, Rg = 100  
IDSQ = 200 mA (RF OFF)2  
ηADD  
ID  
Power Added Efficiency  
Drain Current  
%
50  
A
0.72  
IDSS  
VP  
Saturated Drain Current  
Pinch-Off Voltage  
A
V
2.4  
5
VDS = 2.5 V; VGS = 0 V  
VDS = 2.5 V; ID = 14 mA  
-2.0  
12  
-0.4  
8
RTH  
Thermal Resistance  
°C/W  
Channel to Case  
IGD = 14 mA  
BVGD  
Gate to Drain Breakdown Voltage  
V
Notes:  
1. Pin = 0 dBm  
2. DC performance is tested 100% . Several samples per wafer are tested for RF performance. Wafer rejection criteria for standard devices is 1  
reject for several samples.  
California Eastern Laboratories  

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