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NDT3055L(J23Z) PDF预览

NDT3055L(J23Z)

更新时间: 2024-11-15 23:53:27
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其他 - ETC 晶体晶体管
页数 文件大小 规格书
5页 84K
描述
TRANSISTOR | MOSFET | N-CHANNEL | 60V V(BR)DSS | 3.7A I(D) | SOT-223

NDT3055L(J23Z) 数据手册

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August 1998  
NDT3055L  
N-Channel Logic Level Enhancement Mode Field Effect Transistor  
General Description  
Features  
These logic level N-Channel enhancement mode power  
field effect transistors are produced using Fairchild's  
proprietary, high cell density, DMOS technology. This  
very high density process is especially tailored to  
minimize on-state resistance and provide superior  
switching performance, and withstand high energy pulse  
in the avalanche and commutation modes. These devices  
are particularly suited for low voltage applications such as  
DC motor control and DC/DC conversion where fast  
switching, low in-line power loss, and resistance to  
transients are needed.  
4 A, 60 V. RDS(ON) = 0.100 W @ VGS = 10 V,  
RDS(ON) = 0.120 W @ VGS = 4.5 V.  
Low drive requirements allowing operation directly from logic  
drivers. VGS(TH) < 2V.  
High density cell design for extremely low RDS(ON)  
.
High power and current handling capability in a widely used  
surface mount package.  
SuperSOTTM-3  
SuperSOTTM-8  
SO-8  
SuperSOTTM-6  
SOIC-16  
SOT-223  
D
D
D
D
S
S
D
S
D
S
G
G
G
*
SOT-223  
G
SOT-223  
(J23Z)  
Absolute Maximum Ratings TA = 25oC unless otherwise noted  
Symbol Parameter  
NDT3055L  
Units  
Drain-Source Voltage  
60  
V
VDSS  
VGSS  
ID  
Gate-Source Voltage - Continuous  
±20  
V
A
Maximum Drain Current - Continuous  
- Pulsed  
(Note 1a)  
(Note 1a)  
4
25  
3
PD  
Maximum Power Dissipation  
W
(Note 1b)  
(Note 1c)  
1.3  
1.1  
TJ,TSTG  
Operating and Storage Temperature Range  
-65 to 150  
°C  
THERMAL CHARACTERISTICS  
Thermal Resistance, Junction-to-Ambient (Note 1a)  
Thermal Resistance, Junction-to-Case  
42  
12  
°C/W  
°C/W  
RqJA  
RqJC  
(Note 1)  
* Order option J23Z for cropped center drain lead.  
© 1998 Fairchild Semiconductor Corporation  
NDT3055L Rev.A1  

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