Datasheet > NB7L14MN1G

NB7L14MN1G

更新时间： 2024-11-15 01:12:19

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
12页	148K
描述
Differential 1:4 LVPECL Fanout Buffer

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中文翻译

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NB7L14MN1G 数据手册

NB7L14

2.5V / 3.3V 7GHz/10Gbps

Differential 1:4 LVPECL

Fanout Buffer

Multi−Level Inputs w/ Internal

Termination

www.onsemi.com

MARKING

DIAGRAM*

Description

The NB7L14 is a differential 1:4 LVPECL fanout buffer. The

NB7L14 produces four identical LVPECL output copies of Clock or

Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the

NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and

other Clock or Data distribution applications.

The differential inputs incorporate internal 50 W termination

resistors that are accessed through the VT Pin. This feature allows the

NB7L14 to accept various logic standards, such as LVPECL, CML,

QFN−16

MN SUFFIX

CASE 485G

NB7L

ALYWG

QFN−16

MN SUFFIX

CASE 485AE

7L14

ALYWG

LVDS, LVCMOS or LVTTL logic levels. The V

reference

REFAC

output can be used to rebias capacitor−coupled differential or

single−ended input signals. The 1:4 fanout design was optimized for

low output skew applications.

The NB7L14 is a member of the GigaComm™ family of high

performance clock products.

XXXX = Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Input Data Rate > 10.7 Gb/s

• Input Clock Frequency > 7 GHz

• 165 ps Typical Propagation Delay

• 45 ps Typical Rise and Fall Times

• <15 ps max Output Skew

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

• <0.8 ps maximum RMS Clock Jitter

• <15 ps pp of Data Dependent Jitter

• Differential LVPECL Outputs, 720 mV peak−to−peak, typical

• LVPECL Operating Range: V = 2.375 V to 3.6 V with GND = 0 V

50 W

• NECL Operating Range: V = 0 V with GND = −2.375 V to −3.6 V

• Internal Input Termination Resistors, 50 W

• V

Reference Output

REFAC

50 W

• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,

EP, and SG Devices

• −40°C to +85°C Ambient Operating Temperature

• These are Pb−Free Devices

REFAC

Figure 1. Logic Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

Publication Order Number:

July, 2015 − Rev. 6

NB7L14/D

12 3 4 5 6 7...12

中文翻译

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与NB7L14MN1G相关器件

型号	品牌	获取价格	描述	数据表
NB7L14MN1TWG	ONSEMI	获取价格	Differential 1:4 LVPECL Fanout Buffer
NB7L14MN1TXG	ONSEMI	获取价格	Clock / Data Fanout Buffer, 7 GHz, 1:4 Differential, LVPECL, 2.5 V, 3.3 V, QFN16 3x3, 0.5P
NB7L14MNG	ONSEMI	获取价格	2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer
NB7L14MNTXG	ONSEMI	获取价格	2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer
NB7L1MMNR2	ONSEMI	获取价格	2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output
NB7L1MMNR2G	ONSEMI	获取价格	2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output
NB7L216	ONSEMI	获取价格	2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Transla
NB7L216MN	ONSEMI	获取价格	2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Transla
NB7L216MNG	ONSEMI	获取价格	2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Transla
NB7L216MNR2	ONSEMI	获取价格	2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Transla

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