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NB7L216MNR2G

更新时间： 2024-11-14 03:20:55
品牌 Logo 应用领域
安森美 - ONSEMI 转换器驱动程序和接口接口集成电路时钟
页数 文件大小 规格书
12页 265K
描述
2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination

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中文翻译

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NB7L216MNR2G 技术参数

是否无铅：不含铅生命周期：Lifetime Buy
零件包装代码：QFN包装说明：HVQCCN, LCC16,.12SQ,20
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.13
Is Samacsys：N接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：S-XQCC-N16长度：3 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC16,.12SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：+-2.5/+-3.3 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：Line Driver or Receivers最大压摆率：35 mA
最大供电电压：3.465 V最小供电电压：2.375 V
标称供电电压：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Gold/Palladium (Ni/Au/Pd)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

NB7L216MNR2G 数据手册

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NB7L216  
2.5V/3.3V, 12Gb/s Multi  
Level Clock/Data Input to  
RSECL, High Gain  
Receiver/Buffer/Translator  
with Internal Termination  
http://onsemi.com  
MARKING DIAGRAM*  
Description  
16  
The NB7L216 is a differential receiver/driver with high gain output  
targeted for high frequency applications. The device is functionally  
equivalent to the NBSG16 but with much higher gain output. This  
highly versatile device provides 35 dB of gain up to 7 GHz.  
Inputs incorporate internal 50 W termination resistors and accept  
Negative ECL (NECL), Positive ECL (PECL), LVTTL, LVCMOS,  
CML, or LVDS. Outputs are Reduced Swing ECL (RSECL), 400 mV.  
1
NB7L  
216  
QFN−16  
MN SUFFIX  
CASE 485G  
ALYWG  
G
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
The V pin is an internally generated voltage supply available to  
BB  
= Year  
this device only. V is used as a reference voltage for single−ended  
= Work Week  
= Pb−Free Package  
BB  
NECL or PECL inputs. For all single−ended input conditions, the  
(Note: Microdot may be in either location)  
unused complementary differential input should be connected to V  
BB  
as a switching reference voltage. V may also rebias AC coupled  
BB  
*For additional marking information, refer to  
Application Note AND8002/D.  
inputs. When used, decouple V via a 0.01 mF capacitor and limit  
BB  
current sourcing or sinking to 0.5 mA. When not used, V output  
should be left open.  
BB  
VTD  
Application notes, models and support documentation are available  
at www.onsemi.com.  
50 W  
Q
Q
D
D
Features  
• High Gain of 35 dB from DC to 7 GHz Typical  
• High IIP3: 0 dBm Typical  
50 W  
• 20 mV Minimum Input Voltage Swing  
• Maximum Input Clock Frequency up to 8.5 GHz  
• Maximum Input Data Rate up to 12 Gb/s Typical  
• <0.5 ps of RMS Clock Jitter  
VTD  
Figure 1. Functional Block Diagram  
• <9 ps of Data Dependent Jitter  
• 120 ps Typical Propagation Delay  
• 30 ps Typical Rise and Fall Times  
Device DDJ = 3 ps  
• RSPECL Output with Operating Range: V = 2.375 V to 3.465 V  
CC  
with V = 0 V  
EE  
• RSNECL Output with RSNECL or NECL Inputs with Operating  
Range: V = 0 V with V = −2.375 V to −3.465 V  
CC  
EE  
• RSECL Output Level (400 mV Peak−to−Peak Output),  
• 50 W Internal Input Termination Resistors (Temperature−Coefficient  
of < 6.38 mW/°C)  
• VBB – ECL Reference Voltage Output  
• Pb−Free Packages are Available  
TIME (17 ps/div)  
Figure 2. Typical Output Waveform at  
12 Gb/s with PRBS 223−1 (VINPP = 400 mV,  
Input Signal DDJ = 12 ps)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 11 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
August, 2006 − Rev. 2  
NB7L216/D  
1234567...12

中文翻译

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NB7L216MNR2G 替代型号

型号 品牌 替代类型 描述 数据表
NB7L216MNR2 ONSEMI

完全替代

 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Transla
NB7L216MN ONSEMI

完全替代

 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Transla

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