NB7L72MMNR2G

更新时间： 2024-11-14 05:51:55

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	143K
描述
Multi−Level Inputs w/ Internal Termination

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NB7L72MMNR2G 数据手册

NB7L72M

2.5V / 3.3V Differential 2 x 2

Crosspoint Switch with

CML Outputs Clock/Data

Buffer/Translator

http://onsemi.com

MARKING

Multi−Level Inputs w/ Internal Termination

DIAGRAM*

Description

The NB7L72M is a high bandwidth, low voltage, fully differential

2 x 2 crosspoint switch with CML outputs. The NB7L72M design is

optimized for low skew and minimal jitter as it produces two identical

copies of Clock or Data operating up to 7 GHz or 10 Gb/s,

respectively. As such, the NB7L72M is ideal for SONET, GigE, Fiber

Channel, Backplane and other clock/data distribution applications.

The differential IN/IN inputs incorporate internal 50 W termination

resistors and will accept LVPECL, CML, or LVDS logic levels (see

Figure 11). The 16 mA differential CML outputs provide matching

internal 50 W terminations and produce 400 mV output swings when

NB7L

72M

ALYWG

QFN−16

MN SUFFIX

CASE 485G

= Assembly Location

= Wafer Lot

externally terminated with a 50 W resistor to V (see Figure 9).

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

The NB7L72M is the 2.5 V/3.3 V version of the and NB7V72M and

is offered in a low profile 3x3 mm 16−pin QFN package. Application

notes, models, and support documentation are available at

www.onsemi.com.

The NB7L72M is a member of the GigaComm™ family of high

performance clock products.

*For additional marking information, refer to

Application Note AND8002/D.

Features

SEL0

• Maximum Input Data Rate > 10 Gb/s

• Data Dependent Jitter < 10 ps pk−pk

• Maximum Input Clock Frequency > 7 GHz

• Random Clock Jitter < 0.5 ps RMS, Max

• 150 ps Typical Propagation Delay

• 30 ps Typical Rise and Fall Times

• Differential CML Outputs, 400 mV peak−to−peak, typical

IN0

VT0

IN0

• Operating Range: V = 2.375 V to 3.6 V with GND = 0 V

• Internal 50 W Input Termination Resistors

• QFN−16 Package, 3mm x 3mm

• −40°C to +85°C Ambient Operating Temperature

• These are Pb−Free Devices

IN1

VT1

SEL1

Figure 1. Logic Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

Semiconductor Components Industries, LLC, 2008

Publication Order Number:

September, 2008 − Rev. 1

NB7L72M/D

12 3 4 5 6 7 8

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与NB7L72MMNR2G相关器件

型号	品牌	获取价格	描述	数据表
NB7L72MMNTXG	ONSEMI	获取价格	MultiâLevel Inputs w/ Internal Termination
NB7L86A	ONSEMI	获取价格	2.5 V/3.3 V SiGe Differential Smart Gate with Output Level Select
NB7L86AMNG	ONSEMI	获取价格	2.5 V/3.3 V SiGe Differential Smart Gate with Output Level Select
NB7L86AMNHTBG	ONSEMI	获取价格	2.5 V/3.3 V SiGe Differential Smart Gate with Output Level Select
NB7L86M	ONSEMI	获取价格	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Terminati
NB7L86MMN	ONSEMI	获取价格	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Terminati
NB7L86MMNG	ONSEMI	获取价格	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Terminati
NB7L86MMNR2	ONSEMI	获取价格	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Terminati
NB7L86MMNR2G	ONSEMI	获取价格	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Terminati
NB7LQ572	ONSEMI	获取价格	2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 LVPECL Clock/Data Fanout / Trans

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