Datasheet > NB3W1900LMNG

NB3W1900LMNG

更新时间： 2024-02-20 14:50:12

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
20页	185K
描述
Differential 1:19 HCSL-Compatible PushâPull Clock ZDB/Fanout Buffer

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数据手册

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NB3W1900LMNG 数据手册

NB3W1900L

3.3 V 100/133 MHz

Differential 1:19

HCSL-Compatible Push‐Pull

Clock ZDB/Fanout Buffer for

PCIe^[

www.onsemi.com

Description

The NB3W1900L differential clock buffers are designed to work in

conjunction with a PCIe compliant source clock synthesizer to provide

point-to-point clocks to multiple agents. The device is capable of

1 72

QFN72

MN SUFFIX

CASE 485DK

distributing the reference clocks for Intel QuickPath Interconnect

(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4.The NB3W1900L

internal PLL is optimized to support 100ꢀMHz and 133 MHz

frequency operation. The NB3W1900L is developed with the

low-power NMOS Push-Pull buffer type.

MARKING DIAGRAM

Features

• 19 Low Power Differential Clock Output Pairs @ 0.7 V

• Output-to-Output Skew Performance: < 85 ps

• Cycle-to-Cycle Jitter (PLL Mode): < 50ps

NB3W

1900L

AWLYYWWG

• 100 MHz and 133 MHz PLL Mode to Meet the Next Generation

PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI Phase Jitter

• Input-to-Output Delay Variation: < 50 ps

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb-Free Package

• Fixed-Feedback for Lowest Input-to-Output Delay Variation

• Spread Spectrum Compatible; Tracks Input Clock Spreading for Low

EMI

• Individual OE Control via SMBus

• Low-Power NMOS Push-Pull HCSL−Compatible Outputs

ORDERING INFORMATION

See detailed ordering and shipping information on page 19 of

this data sheet.

• PLL Configurable for PLL Mode or Bypass Mode

(Fanout Operation)

• SMBus Address Configurable to Allow Multiple Buffers in a Single

Control Network

• Programmable PLL Bandwidth

• Two Tri-level Addresses Selection (Nine SMBus Addresses)

• QFN 72-pin Package, 10 mm × 10 mm

• These are Pb-Free Devices

Publication Order Number:

January, 2018 − Rev. 3

NB3W1900L/D

12 3 4 5 6 7...20

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