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NB4L6254D PDF预览

NB4L6254D

更新时间: 2024-09-28 03:46:59
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
9页 137K
描述
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer

NB4L6254D 数据手册

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NB4L6254  
2.5V / 3.3V Differential  
LVPECL 2x2 Clock Switch  
and Low Skew Fanout  
Buffer  
http://onsemi.com  
MARKING  
Description  
The NB4L6254 is a differential 2x2 clock switch and drives  
precisely aligned clock signals through its LVPECL fanout buffers. It  
employs a fully differential architecture with bipolar technology,  
offers superior digital signal characteristics, has very low clock output  
skew and supports clock frequencies from DC up to 3.0 GHz.  
The NB4L6254 is designed for the most demanding, skew critical  
differential clock distribution systems. Typical applications for the  
NB4L6254 are clock distribution, switching and data loopback  
systems of highperformance computer, networking and  
telecommunication systems, as well as onboard clocking of OC3,  
OC12 and OC48 communication systems. In addition, the  
NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL  
fanout buffer.  
DIAGRAM*  
NB4L  
6254  
AWLYYWWG  
LQFP32  
FA SUFFIX  
CASE 873A  
A
= Assembly Location  
WL  
YY  
WW  
G
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
The NB4L6254 can be operated from a single 3.3 V or 2.5 V power  
supply.  
*For additional marking information, refer to  
Application Note AND8002/D.  
Features  
V
CC  
Maximum Clock Input Frequency, 3 GHz  
Maximum Input Data Rate, 3 Gb/s  
Bank A  
QA0  
QA0  
CLK0  
0
1
CLK0  
QA1  
QA1  
QA2  
QA2  
Differential LVPECL Inputs and Outputs  
Low Output Skew: 50 ps Maximum OutputtoOutput Skew  
Synchronous Output Enable Eliminating Output Runt Pulse  
V
CC  
Generation and Metastability  
Bank B  
QB0  
QB0  
QB1  
QB1  
QB2  
QB2  
CLK1  
CLK1  
0
1
Operating Range: Single 3.3 V or 2.5 V Supply  
V
CC  
= 2.375 V to 3.465 V  
LVCMOS Compatible Control Inputs  
Packaged in LQFP32  
Fully Differential Architecture  
40°C to 85°C Ambient Operating Temperature  
These are PbFree Devices*  
SEL0  
SEL1  
OEA  
OEB  
Figure 1. Functional Block Diagram  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
August, 2006 Rev. 1  
NB4L6254/D  

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